PWM波形

verilog编写的简单PWM波形

 

 1 module PWM(clk,rst,outpin);
 2 input clk,rst;
 3 output reg outpin；
 4 
 5 reg [14:0] cnt;
 6 
 7 parameter PULSEWIDTH=25000, PERIOD=50000;//波形周期为PERIOD
 8 
 9 always@(posedge clk or posedge rst )
10   begin
11     if(rst)
12       cnt<=0;
13       else if(cnt==PERIOD)
14              cnt<=15'b0;
15            else
16              cnt<=cnt+1'b1;
17   end
18         
19 always@(posedge clk or posedge rst )
20   begin
21     if(rst)
22       outpin<=0;
23     else  if(cnt<=PULSEWIDTH)
24             outpin<=0;
25            else
26             outpin<=1;   
27     end    
28 endmodule

posted on 2011-09-08 20:32  zerine  阅读(425)  评论(0)    收藏  举报

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