readl(), writel() 函数使用举例

static inline void writeb(unsigned val, unsigned addr)
{

//  首先强制类型转换为  unsigned char *  类型指针，再取这个地址的值， 最后赋值。

    (*(volatile unsigned char *) (addr)) = (val);

 
   
}


static inline unsigned readl(unsigned addr)

{

//  首先强制类型转换为  unsigned char *  类型指针，再取这个地址的值， 最后赋值。同理。

    return (*(volatile unsigned *) (addr));

}

#define MDP_DSI_VIDEO_EN                      (0xAA2F0000)
#define MDP_DSI_VIDEO_HSYNC_CTL               (0xAA2F0004)
#define MDP_DSI_VIDEO_VSYNC_PERIOD            (0xAA2F0008)
#define MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH       (0xAA2F000C)
#define MDP_DSI_VIDEO_DISPLAY_HCTL            (0xAA2F0010)
#define MDP_DSI_VIDEO_DISPLAY_V_START         (0xAA2F0014)
#define MDP_DSI_VIDEO_DISPLAY_V_END           (0xAA2F0018)
#define MDP_DSI_VIDEO_BORDER_CLR              (0xAA2F0028)
#define MDP_DSI_VIDEO_HSYNC_SKEW              (0xAA2F0030)
#define MDP_DSI_VIDEO_CTL_POLARITY            (0xAA2F0038)
#define MDP_DSI_VIDEO_TEST_CTL                (0xAA2F0034)

void config_msm7627a_dsi_video_mode(unsigned short display_wd,
									unsigned short display_ht,
									unsigned short image_wd,
									unsigned short image_ht,
									unsigned short hsync_porch_fp,
									unsigned short hsync_porch_bp,
									unsigned short vsync_porch_fp,
									unsigned short vsync_porch_bp,
									unsigned short hsync_width,
									unsigned short vsync_width,
									unsigned char lane_en)
{

	unsigned char dst_format = 3;	/* RGB888 */
	unsigned char traffic_mode = 2;	/* non burst mode with sync start events */
	unsigned long low_pwr_stop_mode = 1;
	unsigned char eof_bllp_pwr = 0x9;	/* Needed or else will have blank line at top of display */
	unsigned char interleav = 0;

	dprintf(SPEW, "DSI_Video_Mode - Dst Format: RGB888\n");
	dprintf(SPEW, "Traffic mode: burst mode\n");
	dprintf(SPEW, "Data Lane: %d lane\n", lane_en);
// 下面都是用的writel 函数进行寄存器的赋值操作。
	writel(0x00000000, MDP_DSI_VIDEO_EN);
上面这个把MDP_DSI_VIDEO_EN 宏的值写到0x00000000 这个地址的寄存器里面

	writel(0x00000000, DSI_CLK_CTRL);
	writel(0x00000000, DSI_CLK_CTRL);
	writel(0x00000000, DSI_CLK_CTRL);
	writel(0x00000000, DSI_CLK_CTRL);
	writel(0x00000002, DSI_CLK_CTRL);
	writel(0x00000006, DSI_CLK_CTRL);
	writel(0x0000000e, DSI_CLK_CTRL);
	writel(0x0000001e, DSI_CLK_CTRL);
	writel(0x0000003e, DSI_CLK_CTRL);

	writel(0, DSI_CTRL);

	writel(0, DSI_ERR_INT_MASK0);

	writel(0x02020202, DSI_INT_CTRL);

	writel(((hsync_porch_bp + display_wd) << 16) | hsync_porch_bp,
	       DSI_VIDEO_MODE_ACTIVE_H);

	writel(((vsync_porch_bp + display_ht) << 16) | vsync_porch_bp,
	       DSI_VIDEO_MODE_ACTIVE_V);

	writel(((display_ht + vsync_porch_fp + vsync_porch_bp) << 16) |
	       (display_wd + hsync_porch_fp + hsync_porch_bp),
	       DSI_VIDEO_MODE_TOTAL);
	writel((hsync_width) << 16 | 0, DSI_VIDEO_MODE_HSYNC);

	writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC);

	writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS);

	writel(1, DSI_EOT_PACKET_CTRL);

	writel(0x00000100, DSI_MISR_VIDEO_CTRL);

	writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 |
	       eof_bllp_pwr << 12 | traffic_mode << 8 | dst_format << 4 | 0x0,
	       DSI_VIDEO_MODE_CTRL);

	writel(0x67, DSI_CAL_STRENGTH_CTRL);
	writel(0x80006711, DSI_CAL_CTRL);
	writel(0x00010100, DSI_MISR_VIDEO_CTRL);

	writel(0x00010100, DSI_INT_CTRL);
	writel(0x02010202, DSI_INT_CTRL);
	writel(0x02030303, DSI_INT_CTRL);

	writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4