摘要:
module reset_sync (input clk, input reset_in, output reset_out); (* ASYNC_REG = "TRUE" *) reg reset_int = 1'b1; (* ASYNC_REG = "TRUE" *) reg reset_out_tmp = 1'b1; always @(posedge... 阅读全文
posted @ 2018-01-16 16:26
木心的木偶
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