06 2021 档案

【systemverilog】操作符
摘要：== / != / / ! 1 program main ; 2 reg a_1,a_0,a_x,a_z; 3 reg b_1,b_0,b_x,b_z; 4 initial 5 begin 6 a_1 = 'b1;a_0 = 'b0;a_x = 'bx;a_z = 'bz; 7 b_1 = 'b1; 阅读全文

posted @ 2021-06-17 10:49 薛定谔's猫 阅读(419) 评论(0) 推荐(0)

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