-- Quartus VHDL Template
-- Clearable flipflop with enable

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY decoder_3_to_8 IS

 PORT
 (
  a,b,c,g1,g2a,g2b  : IN STD_LOGIC;
  y :OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
 );
 
END decoder_3_to_8;

ARCHITECTURE RTL OF decoder_3_to_8 IS

 SIGNAL indata : STD_LOGIC_VECTOR(2 DOWNTO 0);
 
BEGIN
 indata<=c&b&a;
 PROCESS (indata,g1,g2a,g2b)
 BEGIN
 
  IF(g1='1' AND g2a='0' AND g2b='0')THEN
  
   CASE INDATA IS
    WHEN "000"=>Y<="11111110";
    WHEN "001"=>Y<="11111101";
    WHEN "010"=>Y<="11111011";
    WHEN "011"=>Y<="11110111";
    WHEN "100"=>Y<="11101111";
    WHEN "101"=>Y<="11011111";
    WHEN "110"=>Y<="10111111";
    WHEN "111"=>Y<="01111111";
    WHEN OTHERS=>Y<="XXXXXXXX";
   END CASE; 
  
   ELSE
   
    Y<="11111111";
    
   END IF;  
 
 END PROCESS;  
 
END RTL;