2022-5-19

plans

• test m=4 L=16 case of codec by vcs
• implement by FPGA
• test m=128 and m=256 cases
• implement by FPGA
• improve algorithm----until it is optimal

porcess

verify stating table done!

verify coding process done!

detailed

flow chart

norm frequency

generate codingtable

generate symbolTT and table

detailed data_flow

state table

coding table

symbolTT

decodetable

encoding result

notes:how to transfer bitstream to byte_bitstream

• set up 16bits buff:buff=buff|new_bits
• if nb_bits<8:new_bits<<valid_bits
• if nb_bits>=8:flush buff(>>8),get data_out
• attention:input 10 is trnsfered to 01,it may different in decoding process