校招Verilog——单bit快慢时钟域切换（脉冲展宽法）
1 module Sync_Pulse 2 ( 3 input clka, 4 input clkb, 5 input rst_n, 6 input pulse_ina, //脉冲或电平信号都可以 7 output pulse_outb, //脉冲信号 8 output signal_outb //电平信号 9 ); 10 //-------------------------------------------------------- 11 reg signal_a; 12 reg signal_a_r1; 13 reg signal_a_r2; 14 reg signal_b; 15 reg signal_b_r1; 16 //-------------------------------------------------------- 17 //-- a时钟域生成展宽信号 18 //-------------------------------------------------------- 19 always @(posedge clka or negedge rst_n)begin 20 if(!rst_n)begin 21 signal_a <= 1'b0; 22 end 23 else if(pulse_ina) begin //检测到脉冲 24 signal_a <= 1'b1; //拉高 25 end 26 else if(signal_a_r2) begin //同步到b后同步回a 27 signal_a <= 1'b0; //拉低，展宽使命完成 28 end 29 end 30 //-------------------------------------------------------- 31 //-- 展宽信号同步到b时钟域再同步回a时钟域 32 //-------------------------------------------------------- 33 always @(posedge clkb or negedge rst_n)begin 34 if(!rst_n)begin 35 signal_b <= 1'b0; 36 signal_b_r1 <= 1'b0; 37 end 38 else begin 39 signal_b <= signal_a; 40 signal_b_r1 <= signal_b; 41 end 42 end 43 44 always @(posedge clka or negedge rst_n)begin 45 if(!rst_n)begin 46 signal_a_r1 <= 1'b0; 47 signal_a_r2 <= 1'b0; 48 end 49 else begin 50 signal_a_r1 <= signal_b_r1; 51 signal_a_r2 <= signal_a_r1; 52 end 53 end 54 //-------------------------------------------------------- 55 //-- 脉冲信号输出,上升沿检测 56 //-------------------------------------------------------- 57 assign pulse_outb = ~signal_b_r1 & signal_b; 58 //-------------------------------------------------------- 59 //-- 电平信号输出，b时钟域展宽信号 60 //-------------------------------------------------------- 61 assign signal_outb = signal_b_r1; 62 63 64 endmodule
这个代码建议背出来，看不太懂就自己仿真看看吧！
