校招Verilog——译码器

一、2-4译码器

 1 module Decode_2_4
 2 (
 3     input           [1:0]   indata,
 4     input                   enable_n,
 5     output reg      [3:0]   outdata
 6 );
 7 
 8 always @(*)begin
 9     if(enable_n == 1'b1)
10         outdata = 4'b1111;
11     else begin
12         case(indata)
13             2'b00: outdata = 4'b1110;
14             2'b01: outdata = 4'b1101;
15             2'b10: outdata = 4'b1011;
16             2'b11: outdata = 4'b0111;
17         endcase
18     end
19 end
20 
21 endmodule

 

二、BCD译码器

 1 module Decode_4_10
 2 (
 3     input       [3:0] indata,
 4     output reg  [9:0] outdata
 5 );
 6 
 7 always @(*)begin
 8     case(indata)
 9         4'b0000: outdata = 10'b1111_1111_10;
10         4'b0001: outdata = 10'b1111_1111_01;
11         4'b0010: outdata = 10'b1111_1110_11;
12         4'b0011: outdata = 10'b1111_1101_11;
13         4'b0100: outdata = 10'b1111_1011_11;
14         4'b0101: outdata = 10'b1111_0111_11;
15         4'b0110: outdata = 10'b1110_1111_11;
16         4'b0111: outdata = 10'b1101_1111_11;
17         4'b1000: outdata = 10'b1011_1111_11;
18         4'b1001: outdata = 10'b0111_1111_11;
19         default: outdata = 10'b1111_1111_11;
20     endcase
21 end
22 
23 endmodule

 

posted @ 2020-09-09 20:40  咸鱼IC  阅读(1184)  评论(0)    收藏  举报