1 /********************************************************************
2 *
3 * Standard register and bit definitions for the Texas Instruments
4 * MSP430 microcontroller.
5 *
6 * This file supports assembler and C development for
7 * MSP430G2553 devices.
8 *
9 * Texas Instruments, Version 1.0
10 *
11 * Rev. 1.0, Setup
12 *
13 ********************************************************************/
14
15 #ifndef __MSP430G2553
16 #define __MSP430G2553
17
18 #define __MSP430_HEADER_VERSION__ 1065 /* Beta-Build-Tag: #0023 */
19
20 #ifdef __IAR_SYSTEMS_ICC__
21 #ifndef _SYSTEM_BUILD
22 #pragma system_include
23 #endif
24 #endif
25
26 #if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */
27 #error msp430g2553.h file for use with ICC430/A430 only
28 #endif
29
30
31 #ifdef __IAR_SYSTEMS_ICC__
32 #include "in430.h"
33 #pragma language=extended
34
35 #define DEFC(name, address) __no_init volatile unsigned char name @ address;
36 #define DEFW(name, address) __no_init volatile unsigned short name @ address;
37 #define DEFXC volatile unsigned char
38 #define DEFXW volatile unsigned short
39
40 #endif /* __IAR_SYSTEMS_ICC__ */
41
42
43 #ifdef __IAR_SYSTEMS_ASM__
44 #define DEFC(name, address) sfrb name = address;
45 #define DEFW(name, address) sfrw name = address;
46
47 #endif /* __IAR_SYSTEMS_ASM__*/
48
49 #ifdef __cplusplus
50 #define READ_ONLY
51 #else
52 #define READ_ONLY const
53 #endif
54
55 /************************************************************
56 * STANDARD BITS
57 ************************************************************/
58
59 #define BIT0 (0x0001u)
60 #define BIT1 (0x0002u)
61 #define BIT2 (0x0004u)
62 #define BIT3 (0x0008u)
63 #define BIT4 (0x0010u)
64 #define BIT5 (0x0020u)
65 #define BIT6 (0x0040u)
66 #define BIT7 (0x0080u)
67 #define BIT8 (0x0100u)
68 #define BIT9 (0x0200u)
69 #define BITA (0x0400u)
70 #define BITB (0x0800u)
71 #define BITC (0x1000u)
72 #define BITD (0x2000u)
73 #define BITE (0x4000u)
74 #define BITF (0x8000u)
75
76 /************************************************************
77 * STATUS REGISTER BITS
78 ************************************************************/
79
80 #define C (0x0001u)
81 #define Z (0x0002u)
82 #define N (0x0004u)
83 #define V (0x0100u)
84 #define GIE (0x0008u)
85 #define CPUOFF (0x0010u)
86 #define OSCOFF (0x0020u)
87 #define SCG0 (0x0040u)
88 #define SCG1 (0x0080u)
89
90 /* Low Power Modes coded with Bits 4-7 in SR */
91
92 #ifndef __IAR_SYSTEMS_ICC__ /* Begin #defines for assembler */
93 #define LPM0 (CPUOFF)
94 #define LPM1 (SCG0+CPUOFF)
95 #define LPM2 (SCG1+CPUOFF)
96 #define LPM3 (SCG1+SCG0+CPUOFF)
97 #define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
98 /* End #defines for assembler */
99
100 #else /* Begin #defines for C */
101 #define LPM0_bits (CPUOFF)
102 #define LPM1_bits (SCG0+CPUOFF)
103 #define LPM2_bits (SCG1+CPUOFF)
104 #define LPM3_bits (SCG1+SCG0+CPUOFF)
105 #define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
106
107 #include "in430.h"
108
109 #define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */
110 #define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */
111 #define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */
112 #define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */
113 #define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */
114 #define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */
115 #define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */
116 #define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */
117 #define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */
118 #define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */
119 #endif /* End #defines for C */
120
121 /************************************************************
122 * PERIPHERAL FILE MAP
123 ************************************************************/
124
125 /************************************************************
126 * SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
127 ************************************************************/
128
129 #define IE1_ (0x0000u) /* Interrupt Enable 1 */
130 DEFC( IE1 , IE1_)
131 #define WDTIE (0x01) /* Watchdog Interrupt Enable */
132 #define OFIE (0x02) /* Osc. Fault Interrupt Enable */
133 #define NMIIE (0x10) /* NMI Interrupt Enable */
134 #define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */
135
136 #define IFG1_ (0x0002u) /* Interrupt Flag 1 */
137 DEFC( IFG1 , IFG1_)
138 #define WDTIFG (0x01) /* Watchdog Interrupt Flag */
139 #define OFIFG (0x02) /* Osc. Fault Interrupt Flag */
140 #define PORIFG (0x04) /* Power On Interrupt Flag */
141 #define RSTIFG (0x08) /* Reset Interrupt Flag */
142 #define NMIIFG (0x10) /* NMI Interrupt Flag */
143
144 #define IE2_ (0x0001u) /* Interrupt Enable 2 */
145 DEFC( IE2 , IE2_)
146 #define UC0IE IE2
147 #define UCA0RXIE (0x01)
148 #define UCA0TXIE (0x02)
149 #define UCB0RXIE (0x04)
150 #define UCB0TXIE (0x08)
151
152 #define IFG2_ (0x0003u) /* Interrupt Flag 2 */
153 DEFC( IFG2 , IFG2_)
154 #define UC0IFG IFG2
155 #define UCA0RXIFG (0x01)
156 #define UCA0TXIFG (0x02)
157 #define UCB0RXIFG (0x04)
158 #define UCB0TXIFG (0x08)
159
160 /************************************************************
161 * ADC10
162 ************************************************************/
163 #define __MSP430_HAS_ADC10__ /* Definition to show that Module is available */
164
165 #define ADC10DTC0_ (0x0048u) /* ADC10 Data Transfer Control 0 */
166 DEFC( ADC10DTC0 , ADC10DTC0_)
167 #define ADC10DTC1_ (0x0049u) /* ADC10 Data Transfer Control 1 */
168 DEFC( ADC10DTC1 , ADC10DTC1_)
169 #define ADC10AE0_ (0x004Au) /* ADC10 Analog Enable 0 */
170 DEFC( ADC10AE0 , ADC10AE0_)
171
172 #define ADC10CTL0_ (0x01B0u) /* ADC10 Control 0 */
173 DEFW( ADC10CTL0 , ADC10CTL0_)
174 #define ADC10CTL1_ (0x01B2u) /* ADC10 Control 1 */
175 DEFW( ADC10CTL1 , ADC10CTL1_)
176 #define ADC10MEM_ (0x01B4u) /* ADC10 Memory */
177 DEFW( ADC10MEM , ADC10MEM_)
178 #define ADC10SA_ (0x01BCu) /* ADC10 Data Transfer Start Address */
179 DEFW( ADC10SA , ADC10SA_)
180
181 /* ADC10CTL0 */
182 #define ADC10SC (0x001) /* ADC10 Start Conversion */
183 #define ENC (0x002) /* ADC10 Enable Conversion */
184 #define ADC10IFG (0x004) /* ADC10 Interrupt Flag */
185 #define ADC10IE (0x008) /* ADC10 Interrupt Enalbe */
186 #define ADC10ON (0x010) /* ADC10 On/Enable */
187 #define REFON (0x020) /* ADC10 Reference on */
188 #define REF2_5V (0x040) /* ADC10 Ref 0:1.5V / 1:2.5V */
189 #define MSC (0x080) /* ADC10 Multiple SampleConversion */
190 #define REFBURST (0x100) /* ADC10 Reference Burst Mode */
191 #define REFOUT (0x200) /* ADC10 Enalbe output of Ref. */
192 #define ADC10SR (0x400) /* ADC10 Sampling Rate 0:200ksps / 1:50ksps */
193 #define ADC10SHT0 (0x800) /* ADC10 Sample Hold Select Bit: 0 */
194 #define ADC10SHT1 (0x1000u) /* ADC10 Sample Hold Select Bit: 1 */
195 #define SREF0 (0x2000u) /* ADC10 Reference Select Bit: 0 */
196 #define SREF1 (0x4000u) /* ADC10 Reference Select Bit: 1 */
197 #define SREF2 (0x8000u) /* ADC10 Reference Select Bit: 2 */
198 #define ADC10SHT_0 (0*0x800u) /* 4 x ADC10CLKs */
199 #define ADC10SHT_1 (1*0x800u) /* 8 x ADC10CLKs */
200 #define ADC10SHT_2 (2*0x800u) /* 16 x ADC10CLKs */
201 #define ADC10SHT_3 (3*0x800u) /* 64 x ADC10CLKs */
202
203 #define SREF_0 (0*0x2000u) /* VR+ = AVCC and VR- = AVSS */
204 #define SREF_1 (1*0x2000u) /* VR+ = VREF+ and VR- = AVSS */
205 #define SREF_2 (2*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */
206 #define SREF_3 (3*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */
207 #define SREF_4 (4*0x2000u) /* VR+ = AVCC and VR- = VREF-/VEREF- */
208 #define SREF_5 (5*0x2000u) /* VR+ = VREF+ and VR- = VREF-/VEREF- */
209 #define SREF_6 (6*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */
210 #define SREF_7 (7*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */
211
212 /* ADC10CTL1 */
213 #define ADC10BUSY (0x0001u) /* ADC10 BUSY */
214 #define CONSEQ0 (0x0002u) /* ADC10 Conversion Sequence Select 0 */
215 #define CONSEQ1 (0x0004u) /* ADC10 Conversion Sequence Select 1 */
216 #define ADC10SSEL0 (0x0008u) /* ADC10 Clock Source Select Bit: 0 */
217 #define ADC10SSEL1 (0x0010u) /* ADC10 Clock Source Select Bit: 1 */
218 #define ADC10DIV0 (0x0020u) /* ADC10 Clock Divider Select Bit: 0 */
219 #define ADC10DIV1 (0x0040u) /* ADC10 Clock Divider Select Bit: 1 */
220 #define ADC10DIV2 (0x0080u) /* ADC10 Clock Divider Select Bit: 2 */
221 #define ISSH (0x0100u) /* ADC10 Invert Sample Hold Signal */
222 #define ADC10DF (0x0200u) /* ADC10 Data Format 0:binary 1:2's complement */
223 #define SHS0 (0x0400u) /* ADC10 Sample/Hold Source Bit: 0 */
224 #define SHS1 (0x0800u) /* ADC10 Sample/Hold Source Bit: 1 */
225 #define INCH0 (0x1000u) /* ADC10 Input Channel Select Bit: 0 */
226 #define INCH1 (0x2000u) /* ADC10 Input Channel Select Bit: 1 */
227 #define INCH2 (0x4000u) /* ADC10 Input Channel Select Bit: 2 */
228 #define INCH3 (0x8000u) /* ADC10 Input Channel Select Bit: 3 */
229
230 #define CONSEQ_0 (0*2u) /* Single channel single conversion */
231 #define CONSEQ_1 (1*2u) /* Sequence of channels */
232 #define CONSEQ_2 (2*2u) /* Repeat single channel */
233 #define CONSEQ_3 (3*2u) /* Repeat sequence of channels */
234
235 #define ADC10SSEL_0 (0*8u) /* ADC10OSC */
236 #define ADC10SSEL_1 (1*8u) /* ACLK */
237 #define ADC10SSEL_2 (2*8u) /* MCLK */
238 #define ADC10SSEL_3 (3*8u) /* SMCLK */
239
240 #define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select 0 */
241 #define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select 1 */
242 #define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select 2 */
243 #define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select 3 */
244 #define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select 4 */
245 #define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select 5 */
246 #define ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select 6 */
247 #define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select 7 */
248
249 #define SHS_0 (0*0x400u) /* ADC10SC */
250 #define SHS_1 (1*0x400u) /* TA3 OUT1 */
251 #define SHS_2 (2*0x400u) /* TA3 OUT0 */
252 #define SHS_3 (3*0x400u) /* TA3 OUT2 */
253
254 #define INCH_0 (0*0x1000u) /* Selects Channel 0 */
255 #define INCH_1 (1*0x1000u) /* Selects Channel 1 */
256 #define INCH_2 (2*0x1000u) /* Selects Channel 2 */
257 #define INCH_3 (3*0x1000u) /* Selects Channel 3 */
258 #define INCH_4 (4*0x1000u) /* Selects Channel 4 */
259 #define INCH_5 (5*0x1000u) /* Selects Channel 5 */
260 #define INCH_6 (6*0x1000u) /* Selects Channel 6 */
261 #define INCH_7 (7*0x1000u) /* Selects Channel 7 */
262 #define INCH_8 (8*0x1000u) /* Selects Channel 8 */
263 #define INCH_9 (9*0x1000u) /* Selects Channel 9 */
264 #define INCH_10 (10*0x1000u) /* Selects Channel 10 */
265 #define INCH_11 (11*0x1000u) /* Selects Channel 11 */
266 #define INCH_12 (12*0x1000u) /* Selects Channel 12 */
267 #define INCH_13 (13*0x1000u) /* Selects Channel 13 */
268 #define INCH_14 (14*0x1000u) /* Selects Channel 14 */
269 #define INCH_15 (15*0x1000u) /* Selects Channel 15 */
270
271 /* ADC10DTC0 */
272 #define ADC10FETCH (0x001) /* This bit should normally be reset */
273 #define ADC10B1 (0x002) /* ADC10 block one */
274 #define ADC10CT (0x004) /* ADC10 continuous transfer */
275 #define ADC10TB (0x008) /* ADC10 two-block mode */
276 #define ADC10DISABLE (0x000) /* ADC10DTC1 */
277
278 /************************************************************
279 * Basic Clock Module
280 ************************************************************/
281 #define __MSP430_HAS_BC2__ /* Definition to show that Module is available */
282
283 #define DCOCTL_ (0x0056u) /* DCO Clock Frequency Control */
284 DEFC( DCOCTL , DCOCTL_)
285 #define BCSCTL1_ (0x0057u) /* Basic Clock System Control 1 */
286 DEFC( BCSCTL1 , BCSCTL1_)
287 #define BCSCTL2_ (0x0058u) /* Basic Clock System Control 2 */
288 DEFC( BCSCTL2 , BCSCTL2_)
289 #define BCSCTL3_ (0x0053u) /* Basic Clock System Control 3 */
290 DEFC( BCSCTL3 , BCSCTL3_)
291
292 #define MOD0 (0x01) /* Modulation Bit 0 */
293 #define MOD1 (0x02) /* Modulation Bit 1 */
294 #define MOD2 (0x04) /* Modulation Bit 2 */
295 #define MOD3 (0x08) /* Modulation Bit 3 */
296 #define MOD4 (0x10) /* Modulation Bit 4 */
297 #define DCO0 (0x20) /* DCO Select Bit 0 */
298 #define DCO1 (0x40) /* DCO Select Bit 1 */
299 #define DCO2 (0x80) /* DCO Select Bit 2 */
300
301 #define RSEL0 (0x01) /* Range Select Bit 0 */
302 #define RSEL1 (0x02) /* Range Select Bit 1 */
303 #define RSEL2 (0x04) /* Range Select Bit 2 */
304 #define RSEL3 (0x08) /* Range Select Bit 3 */
305 #define DIVA0 (0x10) /* ACLK Divider 0 */
306 #define DIVA1 (0x20) /* ACLK Divider 1 */
307 #define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */
308 #define XT2OFF (0x80) /* Enable XT2CLK */
309
310 #define DIVA_0 (0x00) /* ACLK Divider 0: /1 */
311 #define DIVA_1 (0x10) /* ACLK Divider 1: /2 */
312 #define DIVA_2 (0x20) /* ACLK Divider 2: /4 */
313 #define DIVA_3 (0x30) /* ACLK Divider 3: /8 */
314
315 #define DIVS0 (0x02) /* SMCLK Divider 0 */
316 #define DIVS1 (0x04) /* SMCLK Divider 1 */
317 #define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */
318 #define DIVM0 (0x10) /* MCLK Divider 0 */
319 #define DIVM1 (0x20) /* MCLK Divider 1 */
320 #define SELM0 (0x40) /* MCLK Source Select 0 */
321 #define SELM1 (0x80) /* MCLK Source Select 1 */
322
323 #define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */
324 #define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */
325 #define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */
326 #define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */
327
328 #define DIVM_0 (0x00) /* MCLK Divider 0: /1 */
329 #define DIVM_1 (0x10) /* MCLK Divider 1: /2 */
330 #define DIVM_2 (0x20) /* MCLK Divider 2: /4 */
331 #define DIVM_3 (0x30) /* MCLK Divider 3: /8 */
332
333 #define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */
334 #define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */
335 #define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */
336 #define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */
337
338 #define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */
339 #define XT2OF (0x02) /* High frequency oscillator 2 fault flag */
340 #define XCAP0 (0x04) /* XIN/XOUT Cap 0 */
341 #define XCAP1 (0x08) /* XIN/XOUT Cap 1 */
342 #define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */
343 #define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */
344 #define XT2S0 (0x40) /* Mode 0 for XT2 */
345 #define XT2S1 (0x80) /* Mode 1 for XT2 */
346
347 #define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */
348 #define XCAP_1 (0x04) /* XIN/XOUT Cap : 6 pF */
349 #define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */
350 #define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5 pF */
351
352 #define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */
353 #define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */
354 #define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */
355 #define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */
356
357 #define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */
358 #define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */
359 #define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */
360 #define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal */
361
362 /************************************************************
363 * Comparator A
364 ************************************************************/
365 #define __MSP430_HAS_CAPLUS__ /* Definition to show that Module is available */
366
367 #define CACTL1_ (0x0059u) /* Comparator A Control 1 */
368 DEFC( CACTL1 , CACTL1_)
369 #define CACTL2_ (0x005Au) /* Comparator A Control 2 */
370 DEFC( CACTL2 , CACTL2_)
371 #define CAPD_ (0x005Bu) /* Comparator A Port Disable */
372 DEFC( CAPD , CAPD_)
373
374 #define CAIFG (0x01) /* Comp. A Interrupt Flag */
375 #define CAIE (0x02) /* Comp. A Interrupt Enable */
376 #define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */
377 #define CAON (0x08) /* Comp. A enable */
378 #define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */
379 #define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */
380 #define CARSEL (0x40) /* Comp. A Internal Reference Enable */
381 #define CAEX (0x80) /* Comp. A Exchange Inputs */
382
383 #define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */
384 #define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
385 #define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
386 #define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/
387
388 #define CAOUT (0x01) /* Comp. A Output */
389 #define CAF (0x02) /* Comp. A Enable Output Filter */
390 #define P2CA0 (0x04) /* Comp. A +Terminal Multiplexer */
391 #define P2CA1 (0x08) /* Comp. A -Terminal Multiplexer */
392 #define P2CA2 (0x10) /* Comp. A -Terminal Multiplexer */
393 #define P2CA3 (0x20) /* Comp. A -Terminal Multiplexer */
394 #define P2CA4 (0x40) /* Comp. A +Terminal Multiplexer */
395 #define CASHORT (0x80) /* Comp. A Short + and - Terminals */
396
397 #define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */
398 #define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */
399 #define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */
400 #define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */
401 #define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */
402 #define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */
403 #define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */
404 #define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */
405
406 /*************************************************************
407 * Flash Memory
408 *************************************************************/
409 #define __MSP430_HAS_FLASH2__ /* Definition to show that Module is available */
410
411 #define FCTL1_ (0x0128u) /* FLASH Control 1 */
412 DEFW( FCTL1 , FCTL1_)
413 #define FCTL2_ (0x012Au) /* FLASH Control 2 */
414 DEFW( FCTL2 , FCTL2_)
415 #define FCTL3_ (0x012Cu) /* FLASH Control 3 */
416 DEFW( FCTL3 , FCTL3_)
417
418 #define FRKEY (0x9600u) /* Flash key returned by read */
419 #define FWKEY (0xA500u) /* Flash key for write */
420 #define FXKEY (0x3300u) /* for use with XOR instruction */
421
422 #define ERASE (0x0002u) /* Enable bit for Flash segment erase */
423 #define MERAS (0x0004u) /* Enable bit for Flash mass erase */
424 #define WRT (0x0040u) /* Enable bit for Flash write */
425 #define BLKWRT (0x0080u) /* Enable bit for Flash segment write */
426 #define SEGWRT (0x0080u) /* old definition */ /* Enable bit for Flash segment write */
427
428 #define FN0 (0x0001u) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
429 #define FN1 (0x0002u) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
430 #ifndef FN2
431 #define FN2 (0x0004u)
432 #endif
433 #ifndef FN3
434 #define FN3 (0x0008u)
435 #endif
436 #ifndef FN4
437 #define FN4 (0x0010u)
438 #endif
439 #define FN5 (0x0020u)
440 #define FSSEL0 (0x0040u) /* Flash clock select 0 */ /* to distinguish from USART SSELx */
441 #define FSSEL1 (0x0080u) /* Flash clock select 1 */
442
443 #define FSSEL_0 (0x0000u) /* Flash clock select: 0 - ACLK */
444 #define FSSEL_1 (0x0040u) /* Flash clock select: 1 - MCLK */
445 #define FSSEL_2 (0x0080u) /* Flash clock select: 2 - SMCLK */
446 #define FSSEL_3 (0x00C0u) /* Flash clock select: 3 - SMCLK */
447
448 #define BUSY (0x0001u) /* Flash busy: 1 */
449 #define KEYV (0x0002u) /* Flash Key violation flag */
450 #define ACCVIFG (0x0004u) /* Flash Access violation flag */
451 #define WAIT (0x0008u) /* Wait flag for segment write */
452 #define LOCK (0x0010u) /* Lock bit: 1 - Flash is locked (read only) */
453 #define EMEX (0x0020u) /* Flash Emergency Exit */
454 #define LOCKA (0x0040u) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
455 #define FAIL (0x0080u) /* Last Program or Erase failed */
456
457 /************************************************************
458 * DIGITAL I/O Port1/2 Pull up / Pull down Resistors
459 ************************************************************/
460 #define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */
461 #define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */
462
463 #define P1IN_ (0x0020u) /* Port 1 Input */
464 READ_ONLY DEFC( P1IN , P1IN_)
465 #define P1OUT_ (0x0021u) /* Port 1 Output */
466 DEFC( P1OUT , P1OUT_)
467 #define P1DIR_ (0x0022u) /* Port 1 Direction */
468 DEFC( P1DIR , P1DIR_)
469 #define P1IFG_ (0x0023u) /* Port 1 Interrupt Flag */
470 DEFC( P1IFG , P1IFG_)
471 #define P1IES_ (0x0024u) /* Port 1 Interrupt Edge Select */
472 DEFC( P1IES , P1IES_)
473 #define P1IE_ (0x0025u) /* Port 1 Interrupt Enable */
474 DEFC( P1IE , P1IE_)
475 #define P1SEL_ (0x0026u) /* Port 1 Selection */
476 DEFC( P1SEL , P1SEL_)
477 #define P1SEL2_ (0x0041u) /* Port 1 Selection 2 */
478 DEFC( P1SEL2 , P1SEL2_)
479 #define P1REN_ (0x0027u) /* Port 1 Resistor Enable */
480 DEFC( P1REN , P1REN_)
481
482 #define P2IN_ (0x0028u) /* Port 2 Input */
483 READ_ONLY DEFC( P2IN , P2IN_)
484 #define P2OUT_ (0x0029u) /* Port 2 Output */
485 DEFC( P2OUT , P2OUT_)
486 #define P2DIR_ (0x002Au) /* Port 2 Direction */
487 DEFC( P2DIR , P2DIR_)
488 #define P2IFG_ (0x002Bu) /* Port 2 Interrupt Flag */
489 DEFC( P2IFG , P2IFG_)
490 #define P2IES_ (0x002Cu) /* Port 2 Interrupt Edge Select */
491 DEFC( P2IES , P2IES_)
492 #define P2IE_ (0x002Du) /* Port 2 Interrupt Enable */
493 DEFC( P2IE , P2IE_)
494 #define P2SEL_ (0x002Eu) /* Port 2 Selection */
495 DEFC( P2SEL , P2SEL_)
496 #define P2SEL2_ (0x0042u) /* Port 2 Selection 2 */
497 DEFC( P2SEL2 , P2SEL2_)
498 #define P2REN_ (0x002Fu) /* Port 2 Resistor Enable */
499 DEFC( P2REN , P2REN_)
500
501 /************************************************************
502 * DIGITAL I/O Port3 Pull up / Pull down Resistors
503 ************************************************************/
504 #define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */
505
506 #define P3IN_ (0x0018u) /* Port 3 Input */
507 READ_ONLY DEFC( P3IN , P3IN_)
508 #define P3OUT_ (0x0019u) /* Port 3 Output */
509 DEFC( P3OUT , P3OUT_)
510 #define P3DIR_ (0x001Au) /* Port 3 Direction */
511 DEFC( P3DIR , P3DIR_)
512 #define P3SEL_ (0x001Bu) /* Port 3 Selection */
513 DEFC( P3SEL , P3SEL_)
514 #define P3SEL2_ (0x0043u) /* Port 3 Selection 2 */
515 DEFC( P3SEL2 , P3SEL2_)
516 #define P3REN_ (0x0010u) /* Port 3 Resistor Enable */
517 DEFC( P3REN , P3REN_)
518
519 /************************************************************
520 * Timer0_A3
521 ************************************************************/
522 #define __MSP430_HAS_TA3__ /* Definition to show that Module is available */
523
524 #define TA0IV_ (0x012Eu) /* Timer0_A3 Interrupt Vector Word */
525 READ_ONLY DEFW( TA0IV , TA0IV_)
526 #define TA0CTL_ (0x0160u) /* Timer0_A3 Control */
527 DEFW( TA0CTL , TA0CTL_)
528 #define TA0CCTL0_ (0x0162u) /* Timer0_A3 Capture/Compare Control 0 */
529 DEFW( TA0CCTL0 , TA0CCTL0_)
530 #define TA0CCTL1_ (0x0164u) /* Timer0_A3 Capture/Compare Control 1 */
531 DEFW( TA0CCTL1 , TA0CCTL1_)
532 #define TA0CCTL2_ (0x0166u) /* Timer0_A3 Capture/Compare Control 2 */
533 DEFW( TA0CCTL2 , TA0CCTL2_)
534 #define TA0R_ (0x0170u) /* Timer0_A3 */
535 DEFW( TA0R , TA0R_)
536 #define TA0CCR0_ (0x0172u) /* Timer0_A3 Capture/Compare 0 */
537 DEFW( TA0CCR0 , TA0CCR0_)
538 #define TA0CCR1_ (0x0174u) /* Timer0_A3 Capture/Compare 1 */
539 DEFW( TA0CCR1 , TA0CCR1_)
540 #define TA0CCR2_ (0x0176u) /* Timer0_A3 Capture/Compare 2 */
541 DEFW( TA0CCR2 , TA0CCR2_)
542
543 /* Alternate register names */
544 #define TAIV TA0IV /* Timer A Interrupt Vector Word */
545 #define TACTL TA0CTL /* Timer A Control */
546 #define TACCTL0 TA0CCTL0 /* Timer A Capture/Compare Control 0 */
547 #define TACCTL1 TA0CCTL1 /* Timer A Capture/Compare Control 1 */
548 #define TACCTL2 TA0CCTL2 /* Timer A Capture/Compare Control 2 */
549 #define TAR TA0R /* Timer A */
550 #define TACCR0 TA0CCR0 /* Timer A Capture/Compare 0 */
551 #define TACCR1 TA0CCR1 /* Timer A Capture/Compare 1 */
552 #define TACCR2 TA0CCR2 /* Timer A Capture/Compare 2 */
553 #define TAIV_ TA0IV_ /* Timer A Interrupt Vector Word */
554 #define TACTL_ TA0CTL_ /* Timer A Control */
555 #define TACCTL0_ TA0CCTL0_ /* Timer A Capture/Compare Control 0 */
556 #define TACCTL1_ TA0CCTL1_ /* Timer A Capture/Compare Control 1 */
557 #define TACCTL2_ TA0CCTL2_ /* Timer A Capture/Compare Control 2 */
558 #define TAR_ TA0R_ /* Timer A */
559 #define TACCR0_ TA0CCR0_ /* Timer A Capture/Compare 0 */
560 #define TACCR1_ TA0CCR1_ /* Timer A Capture/Compare 1 */
561 #define TACCR2_ TA0CCR2_ /* Timer A Capture/Compare 2 */
562
563 /* Alternate register names 2 */
564 #define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
565 #define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
566 #define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
567 #define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
568 #define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
569 #define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
570 #define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
571 #define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
572 #define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
573 #define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
574 #define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
575 #define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
576
577 #define TASSEL1 (0x0200u) /* Timer A clock source select 1 */
578 #define TASSEL0 (0x0100u) /* Timer A clock source select 0 */
579 #define ID1 (0x0080u) /* Timer A clock input divider 1 */
580 #define ID0 (0x0040u) /* Timer A clock input divider 0 */
581 #define MC1 (0x0020u) /* Timer A mode control 1 */
582 #define MC0 (0x0010u) /* Timer A mode control 0 */
583 #define TACLR (0x0004u) /* Timer A counter clear */
584 #define TAIE (0x0002u) /* Timer A counter interrupt enable */
585 #define TAIFG (0x0001u) /* Timer A counter interrupt flag */
586
587 #define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
588 #define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
589 #define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */
590 #define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
591 #define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
592 #define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
593 #define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
594 #define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
595 #define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
596 #define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
597 #define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
598 #define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
599
600 #define CM1 (0x8000u) /* Capture mode 1 */
601 #define CM0 (0x4000u) /* Capture mode 0 */
602 #define CCIS1 (0x2000u) /* Capture input select 1 */
603 #define CCIS0 (0x1000u) /* Capture input select 0 */
604 #define SCS (0x0800u) /* Capture sychronize */
605 #define SCCI (0x0400u) /* Latched capture signal (read) */
606 #define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */
607 #define OUTMOD2 (0x0080u) /* Output mode 2 */
608 #define OUTMOD1 (0x0040u) /* Output mode 1 */
609 #define OUTMOD0 (0x0020u) /* Output mode 0 */
610 #define CCIE (0x0010u) /* Capture/compare interrupt enable */
611 #define CCI (0x0008u) /* Capture input signal (read) */
612 #define OUT (0x0004u) /* PWM Output signal if output mode 0 */
613 #define COV (0x0002u) /* Capture/compare overflow flag */
614 #define CCIFG (0x0001u) /* Capture/compare interrupt flag */
615
616 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
617 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
618 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
619 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
620 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
621 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
622 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
623 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
624 #define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
625 #define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
626 #define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
627 #define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
628 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
629 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
630 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
631 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
632
633 /* T0_A3IV Definitions */
634 #define TA0IV_NONE (0x0000u) /* No Interrupt pending */
635 #define TA0IV_TACCR1 (0x0002u) /* TA0CCR1_CCIFG */
636 #define TA0IV_TACCR2 (0x0004u) /* TA0CCR2_CCIFG */
637 #define TA0IV_6 (0x0006u) /* Reserved */
638 #define TA0IV_8 (0x0008u) /* Reserved */
639 #define TA0IV_TAIFG (0x000Au) /* TA0IFG */
640
641 /************************************************************
642 * Timer1_A3
643 ************************************************************/
644 #define __MSP430_HAS_T1A3__ /* Definition to show that Module is available */
645
646 #define TA1IV_ (0x011Eu) /* Timer1_A3 Interrupt Vector Word */
647 READ_ONLY DEFW( TA1IV , TA1IV_)
648 #define TA1CTL_ (0x0180u) /* Timer1_A3 Control */
649 DEFW( TA1CTL , TA1CTL_)
650 #define TA1CCTL0_ (0x0182u) /* Timer1_A3 Capture/Compare Control 0 */
651 DEFW( TA1CCTL0 , TA1CCTL0_)
652 #define TA1CCTL1_ (0x0184u) /* Timer1_A3 Capture/Compare Control 1 */
653 DEFW( TA1CCTL1 , TA1CCTL1_)
654 #define TA1CCTL2_ (0x0186u) /* Timer1_A3 Capture/Compare Control 2 */
655 DEFW( TA1CCTL2 , TA1CCTL2_)
656 #define TA1R_ (0x0190u) /* Timer1_A3 */
657 DEFW( TA1R , TA1R_)
658 #define TA1CCR0_ (0x0192u) /* Timer1_A3 Capture/Compare 0 */
659 DEFW( TA1CCR0 , TA1CCR0_)
660 #define TA1CCR1_ (0x0194u) /* Timer1_A3 Capture/Compare 1 */
661 DEFW( TA1CCR1 , TA1CCR1_)
662 #define TA1CCR2_ (0x0196u) /* Timer1_A3 Capture/Compare 2 */
663 DEFW( TA1CCR2 , TA1CCR2_)
664
665 /* Bits are already defined within the Timer0_Ax */
666
667 /* T1_A3IV Definitions */
668 #define TA1IV_NONE (0x0000u) /* No Interrupt pending */
669 #define TA1IV_TACCR1 (0x0002u) /* TA1CCR1_CCIFG */
670 #define TA1IV_TACCR2 (0x0004u) /* TA1CCR2_CCIFG */
671 #define TA1IV_TAIFG (0x000Au) /* TA1IFG */
672
673 /************************************************************
674 * USCI
675 ************************************************************/
676 #define __MSP430_HAS_USCI__ /* Definition to show that Module is available */
677
678 #define UCA0CTL0_ (0x0060u) /* USCI A0 Control Register 0 */
679 DEFC( UCA0CTL0 , UCA0CTL0_)
680 #define UCA0CTL1_ (0x0061u) /* USCI A0 Control Register 1 */
681 DEFC( UCA0CTL1 , UCA0CTL1_)
682 #define UCA0BR0_ (0x0062u) /* USCI A0 Baud Rate 0 */
683 DEFC( UCA0BR0 , UCA0BR0_)
684 #define UCA0BR1_ (0x0063u) /* USCI A0 Baud Rate 1 */
685 DEFC( UCA0BR1 , UCA0BR1_)
686 #define UCA0MCTL_ (0x0064u) /* USCI A0 Modulation Control */
687 DEFC( UCA0MCTL , UCA0MCTL_)
688 #define UCA0STAT_ (0x0065u) /* USCI A0 Status Register */
689 DEFC( UCA0STAT , UCA0STAT_)
690 #define UCA0RXBUF_ (0x0066u) /* USCI A0 Receive Buffer */
691 READ_ONLY DEFC( UCA0RXBUF , UCA0RXBUF_)
692 #define UCA0TXBUF_ (0x0067u) /* USCI A0 Transmit Buffer */
693 DEFC( UCA0TXBUF , UCA0TXBUF_)
694 #define UCA0ABCTL_ (0x005Du) /* USCI A0 LIN Control */
695 DEFC( UCA0ABCTL , UCA0ABCTL_)
696 #define UCA0IRTCTL_ (0x005Eu) /* USCI A0 IrDA Transmit Control */
697 DEFC( UCA0IRTCTL , UCA0IRTCTL_)
698 #define UCA0IRRCTL_ (0x005Fu) /* USCI A0 IrDA Receive Control */
699 DEFC( UCA0IRRCTL , UCA0IRRCTL_)
700
701
702
703 #define UCB0CTL0_ (0x0068u) /* USCI B0 Control Register 0 */
704 DEFC( UCB0CTL0 , UCB0CTL0_)
705 #define UCB0CTL1_ (0x0069u) /* USCI B0 Control Register 1 */
706 DEFC( UCB0CTL1 , UCB0CTL1_)
707 #define UCB0BR0_ (0x006Au) /* USCI B0 Baud Rate 0 */
708 DEFC( UCB0BR0 , UCB0BR0_)
709 #define UCB0BR1_ (0x006Bu) /* USCI B0 Baud Rate 1 */
710 DEFC( UCB0BR1 , UCB0BR1_)
711 #define UCB0I2CIE_ (0x006Cu) /* USCI B0 I2C Interrupt Enable Register */
712 DEFC( UCB0I2CIE , UCB0I2CIE_)
713 #define UCB0STAT_ (0x006Du) /* USCI B0 Status Register */
714 DEFC( UCB0STAT , UCB0STAT_)
715 #define UCB0RXBUF_ (0x006Eu) /* USCI B0 Receive Buffer */
716 READ_ONLY DEFC( UCB0RXBUF , UCB0RXBUF_)
717 #define UCB0TXBUF_ (0x006Fu) /* USCI B0 Transmit Buffer */
718 DEFC( UCB0TXBUF , UCB0TXBUF_)
719 #define UCB0I2COA_ (0x0118u) /* USCI B0 I2C Own Address */
720 DEFW( UCB0I2COA , UCB0I2COA_)
721 #define UCB0I2CSA_ (0x011Au) /* USCI B0 I2C Slave Address */
722 DEFW( UCB0I2CSA , UCB0I2CSA_)
723
724 // UART-Mode Bits
725 #define UCPEN (0x80) /* Async. Mode: Parity enable */
726 #define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */
727 #define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */
728 #define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
729 #define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */
730 #define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */
731 #define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */
732 #define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
733
734 // SPI-Mode Bits
735 #define UCCKPH (0x80) /* Sync. Mode: Clock Phase */
736 #define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */
737 #define UCMST (0x08) /* Sync. Mode: Master Select */
738
739 // I2C-Mode Bits
740 #define UCA10 (0x80) /* 10-bit Address Mode */
741 #define UCSLA10 (0x40) /* 10-bit Slave Address Mode */
742 #define UCMM (0x20) /* Multi-Master Environment */
743 //#define res (0x10) /* reserved */
744 #define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */
745 #define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */
746 #define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */
747 #define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */
748
749 // UART-Mode Bits
750 #define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */
751 #define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */
752 #define UCRXEIE (0x20) /* RX Error interrupt enable */
753 #define UCBRKIE (0x10) /* Break interrupt enable */
754 #define UCDORM (0x08) /* Dormant (Sleep) Mode */
755 #define UCTXADDR (0x04) /* Send next Data as Address */
756 #define UCTXBRK (0x02) /* Send next Data as Break */
757 #define UCSWRST (0x01) /* USCI Software Reset */
758
759 // SPI-Mode Bits
760 //#define res (0x20) /* reserved */
761 //#define res (0x10) /* reserved */
762 //#define res (0x08) /* reserved */
763 //#define res (0x04) /* reserved */
764 //#define res (0x02) /* reserved */
765
766 // I2C-Mode Bits
767 //#define res (0x20) /* reserved */
768 #define UCTR (0x10) /* Transmit/Receive Select/Flag */
769 #define UCTXNACK (0x08) /* Transmit NACK */
770 #define UCTXSTP (0x04) /* Transmit STOP */
771 #define UCTXSTT (0x02) /* Transmit START */
772 #define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */
773 #define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */
774 #define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */
775 #define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */
776
777 #define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */
778 #define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */
779 #define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */
780 #define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */
781 #define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */
782 #define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */
783 #define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */
784 #define UCOS16 (0x01) /* USCI 16-times Oversampling enable */
785
786 #define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
787 #define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
788 #define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
789 #define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
790 #define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
791 #define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
792 #define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
793 #define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
794 #define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
795 #define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
796 #define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
797 #define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
798 #define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
799 #define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
800 #define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
801 #define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
802
803 #define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */
804 #define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */
805 #define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */
806 #define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */
807 #define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */
808 #define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */
809 #define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */
810 #define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */
811
812 #define UCLISTEN (0x80) /* USCI Listen mode */
813 #define UCFE (0x40) /* USCI Frame Error Flag */
814 #define UCOE (0x20) /* USCI Overrun Error Flag */
815 #define UCPE (0x10) /* USCI Parity Error Flag */
816 #define UCBRK (0x08) /* USCI Break received */
817 #define UCRXERR (0x04) /* USCI RX Error Flag */
818 #define UCADDR (0x02) /* USCI Address received Flag */
819 #define UCBUSY (0x01) /* USCI Busy Flag */
820 #define UCIDLE (0x02) /* USCI Idle line detected Flag */
821
822 //#define res (0x80) /* reserved */
823 //#define res (0x40) /* reserved */
824 //#define res (0x20) /* reserved */
825 //#define res (0x10) /* reserved */
826 #define UCNACKIE (0x08) /* NACK Condition interrupt enable */
827 #define UCSTPIE (0x04) /* STOP Condition interrupt enable */
828 #define UCSTTIE (0x02) /* START Condition interrupt enable */
829 #define UCALIE (0x01) /* Arbitration Lost interrupt enable */
830
831 #define UCSCLLOW (0x40) /* SCL low */
832 #define UCGC (0x20) /* General Call address received Flag */
833 #define UCBBUSY (0x10) /* Bus Busy Flag */
834 #define UCNACKIFG (0x08) /* NAK Condition interrupt Flag */
835 #define UCSTPIFG (0x04) /* STOP Condition interrupt Flag */
836 #define UCSTTIFG (0x02) /* START Condition interrupt Flag */
837 #define UCALIFG (0x01) /* Arbitration Lost interrupt Flag */
838
839 #define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */
840 #define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */
841 #define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */
842 #define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */
843 #define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */
844 #define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */
845 #define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */
846 #define UCIREN (0x01) /* IRDA Encoder/Decoder enable */
847
848 #define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */
849 #define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */
850 #define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */
851 #define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */
852 #define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */
853 #define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */
854 #define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */
855 #define UCIRRXFE (0x01) /* IRDA Receive Filter enable */
856
857 //#define res (0x80) /* reserved */
858 //#define res (0x40) /* reserved */
859 #define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
860 #define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
861 #define UCSTOE (0x08) /* Sync-Field Timeout error */
862 #define UCBTOE (0x04) /* Break Timeout error */
863 //#define res (0x02) /* reserved */
864 #define UCABDEN (0x01) /* Auto Baud Rate detect enable */
865
866 #define UCGCEN (0x8000u) /* I2C General Call enable */
867 #define UCOA9 (0x0200u) /* I2C Own Address 9 */
868 #define UCOA8 (0x0100u) /* I2C Own Address 8 */
869 #define UCOA7 (0x0080u) /* I2C Own Address 7 */
870 #define UCOA6 (0x0040u) /* I2C Own Address 6 */
871 #define UCOA5 (0x0020u) /* I2C Own Address 5 */
872 #define UCOA4 (0x0010u) /* I2C Own Address 4 */
873 #define UCOA3 (0x0008u) /* I2C Own Address 3 */
874 #define UCOA2 (0x0004u) /* I2C Own Address 2 */
875 #define UCOA1 (0x0002u) /* I2C Own Address 1 */
876 #define UCOA0 (0x0001u) /* I2C Own Address 0 */
877
878 #define UCSA9 (0x0200u) /* I2C Slave Address 9 */
879 #define UCSA8 (0x0100u) /* I2C Slave Address 8 */
880 #define UCSA7 (0x0080u) /* I2C Slave Address 7 */
881 #define UCSA6 (0x0040u) /* I2C Slave Address 6 */
882 #define UCSA5 (0x0020u) /* I2C Slave Address 5 */
883 #define UCSA4 (0x0010u) /* I2C Slave Address 4 */
884 #define UCSA3 (0x0008u) /* I2C Slave Address 3 */
885 #define UCSA2 (0x0004u) /* I2C Slave Address 2 */
886 #define UCSA1 (0x0002u) /* I2C Slave Address 1 */
887 #define UCSA0 (0x0001u) /* I2C Slave Address 0 */
888
889 /************************************************************
890 * WATCHDOG TIMER
891 ************************************************************/
892 #define __MSP430_HAS_WDT__ /* Definition to show that Module is available */
893
894 #define WDTCTL_ (0x0120u) /* Watchdog Timer Control */
895 DEFW( WDTCTL , WDTCTL_)
896 /* The bit names have been prefixed with "WDT" */
897 #define WDTIS0 (0x0001u)
898 #define WDTIS1 (0x0002u)
899 #define WDTSSEL (0x0004u)
900 #define WDTCNTCL (0x0008u)
901 #define WDTTMSEL (0x0010u)
902 #define WDTNMI (0x0020u)
903 #define WDTNMIES (0x0040u)
904 #define WDTHOLD (0x0080u)
905
906 #define WDTPW (0x5A00u)
907
908 /* WDT-interval times [1ms] coded with Bits 0-2 */
909 /* WDT is clocked by fSMCLK (assumed 1MHz) */
910 #define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */
911 #define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */
912 #define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */
913 #define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
914 /* WDT is clocked by fACLK (assumed 32KHz) */
915 #define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */
916 #define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
917 #define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
918 #define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
919 /* Watchdog mode -> reset after expired time */
920 /* WDT is clocked by fSMCLK (assumed 1MHz) */
921 #define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */
922 #define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */
923 #define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */
924 #define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
925 /* WDT is clocked by fACLK (assumed 32KHz) */
926 #define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */
927 #define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
928 #define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
929 #define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
930
931 /* INTERRUPT CONTROL */
932 /* These two bits are defined in the Special Function Registers */
933 /* #define WDTIE 0x01 */
934 /* #define WDTIFG 0x01 */
935
936 /************************************************************
937 * Calibration Data in Info Mem
938 ************************************************************/
939
940 #ifndef __DisableCalData
941
942 #define CALDCO_16MHZ_ (0x10F8u) /* DCOCTL Calibration Data for 16MHz */
943 READ_ONLY DEFC( CALDCO_16MHZ , CALDCO_16MHZ_)
944 #define CALBC1_16MHZ_ (0x10F9u) /* BCSCTL1 Calibration Data for 16MHz */
945 READ_ONLY DEFC( CALBC1_16MHZ , CALBC1_16MHZ_)
946 #define CALDCO_12MHZ_ (0x10FAu) /* DCOCTL Calibration Data for 12MHz */
947 READ_ONLY DEFC( CALDCO_12MHZ , CALDCO_12MHZ_)
948 #define CALBC1_12MHZ_ (0x10FBu) /* BCSCTL1 Calibration Data for 12MHz */
949 READ_ONLY DEFC( CALBC1_12MHZ , CALBC1_12MHZ_)
950 #define CALDCO_8MHZ_ (0x10FCu) /* DCOCTL Calibration Data for 8MHz */
951 READ_ONLY DEFC( CALDCO_8MHZ , CALDCO_8MHZ_)
952 #define CALBC1_8MHZ_ (0x10FDu) /* BCSCTL1 Calibration Data for 8MHz */
953 READ_ONLY DEFC( CALBC1_8MHZ , CALBC1_8MHZ_)
954 #define CALDCO_1MHZ_ (0x10FEu) /* DCOCTL Calibration Data for 1MHz */
955 READ_ONLY DEFC( CALDCO_1MHZ , CALDCO_1MHZ_)
956 #define CALBC1_1MHZ_ (0x10FFu) /* BCSCTL1 Calibration Data for 1MHz */
957 READ_ONLY DEFC( CALBC1_1MHZ , CALBC1_1MHZ_)
958
959 #endif /* #ifndef __DisableCalData */
960
961 /************************************************************
962 * Interrupt Vectors (offset from 0xFFE0)
963 ************************************************************/
964
965 #define PORT1_VECTOR (2 * 2u) /* 0xFFE4 Port 1 */
966 #define PORT2_VECTOR (3 * 2u) /* 0xFFE6 Port 2 */
967 #define ADC10_VECTOR (5 * 2u) /* 0xFFEA ADC10 */
968 #define USCIAB0TX_VECTOR (6 * 2u) /* 0xFFEC USCI A0/B0 Transmit */
969 #define USCIAB0RX_VECTOR (7 * 2u) /* 0xFFEE USCI A0/B0 Receive */
970 #define TIMER0_A1_VECTOR (8 * 2u) /* 0xFFF0 Timer0)A CC1, TA0 */
971 #define TIMER0_A0_VECTOR (9 * 2u) /* 0xFFF2 Timer0_A CC0 */
972 #define WDT_VECTOR (10 * 2u) /* 0xFFF4 Watchdog Timer */
973 #define COMPARATORA_VECTOR (11 * 2u) /* 0xFFF6 Comparator A */
974 #define TIMER1_A1_VECTOR (12 * 2u) /* 0xFFF8 Timer1_A CC1-4, TA1 */
975 #define TIMER1_A0_VECTOR (13 * 2u) /* 0xFFFA Timer1_A CC0 */
976 #define NMI_VECTOR (14 * 2u) /* 0xFFFC Non-maskable */
977 #define RESET_VECTOR (15 * 2u) /* 0xFFFE Reset [Highest Priority] */
978
979 /************************************************************
980 * End of Modules
981 ************************************************************/
982 #pragma language=default
983
984 #endif /* #ifndef __MSP430G2553 */
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