FPGA实现分频器

`timescale 1ns/1ns

module  fpq_tb();


reg [0:0]  sys_clk;
reg [0:0]  sys_rst_n;
wire [0:0] clk_out;

initial begin
          sys_clk=1'b0;
          sys_rst_n=1'b0;
          #50;
          sys_rst_n=1;  
          #500;
          $stop;
        end
        
        
always #10   sys_clk<=~sys_clk ;  


 divider
#(
.DIV_PARAMETER(8'D7)
)
u_divider
(
             .sys_clk    (sys_clk),
             .sys_rst_n  (sys_rst_n),
             .clk_out    (clk_out)

);



endmodule

module  divider
#(
parameter[7:0] DIV_PARAMETER = 8'D2
)
(
             input  wire  [0:0] sys_clk ,
             input  wire  [0:0] sys_rst_n,
             output wire   [0:0] clk_out

);

localparam [7:0] DIV_MAX_ODD =DIV_PARAMETER/2-8'd1 ;
localparam [7:0] DIV_EVEN =DIV_PARAMETER/2;

reg [7:0] odd_cnt;
reg [7:0] even_cnt;
reg [0:0] clk_odd_out;
reg [0:0] clk_even_1;
reg [0:0] clk_even_2;


//对偶分频的时钟进行计数
always @(posedge sys_clk or negedge sys_rst_n )
     begin
        if(sys_rst_n==1'b0)
            odd_cnt<=8'd0;
        else if(odd_cnt>=DIV_MAX_ODD)
            odd_cnt<=8'd0;
        else 
            odd_cnt<=odd_cnt+8'd1;       
     end
//当偶分频的时钟计数到达分频系数的一半时，对偶分频时钟进行翻转
always @(posedge sys_clk or negedge sys_rst_n )
     begin
        if(sys_rst_n==1'b0)
           clk_odd_out<=1'b0;
        else if(odd_cnt>=DIV_MAX_ODD)
           clk_odd_out<=~clk_odd_out;
        else 
            clk_odd_out<=clk_odd_out;       
     end
//对奇分频的时钟进行计数到达分频系数减1时归零    
always @(posedge sys_clk or negedge sys_rst_n )
     begin
        if(sys_rst_n==1'b0)
            even_cnt<=8'd0;
        else if(even_cnt>=DIV_PARAMETER-8'd1)
            even_cnt<=8'd0;
        else 
            even_cnt<=even_cnt+8'd1;       
     end    
//在posedge sys_clk对奇分频的计数到达分频系数一半时clk_even_1拉高，当到达分频系数减1时clk_even_1拉低，其它时候不变   
always @(posedge sys_clk or negedge sys_rst_n )
     begin
        if(sys_rst_n==1'b0)
            clk_even_1<=1'b0;
        else if(even_cnt==DIV_EVEN)
            clk_even_1<=1'b1;
        else if(even_cnt>=DIV_PARAMETER-8'd1)   
            clk_even_1<=1'b0;
        else 
             clk_even_1<=clk_even_1;    
        
     end
//在negedge sys_clk对奇分频的计数到达分频系数一半时clk_even_1拉高，当到达分频系数减1时clk_even_1拉低，其它时候不变      
always @(negedge sys_clk or negedge sys_rst_n )
     begin
        if(sys_rst_n==1'b0)
            clk_even_2<=1'b0;
        else if(even_cnt==DIV_EVEN)
            clk_even_2<=1'b1;
        else if(even_cnt>=DIV_PARAMETER-8'd1)   
            clk_even_2<=1'b0;
        else 
             clk_even_2<=clk_even_2;    
        
     end   
 
assign clk_out =(DIV_PARAMETER%2)? (clk_even_1|clk_even_2): clk_odd_out;    
   
endmodule