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中国计算机学会推荐国际学术会议 (硬件设计相关)

CCF等级 会议简称 会议全称 出版社 网址 华科集成毕业条件认定
A DAC Design Automation Conference ACM https://dblp.uni-trier.de/db/conf/dac/ A
A ASPLOS International Conference on Architectural Support for Programming Languages and Operating Systems ACM http://dblp.uni-trier.de/db/conf/asplos/ -
A ISCA International Symposium on Computer Architecture ACM/IEEE http://dblp.uni-trier.de/db/conf/isca/ -
A MICRO IEEE/ACM International Symposium on Microarchitecture IEEE/ACM https://dblp.uni-trier.de/db/conf/micro/index.html A
A HPCA IEEE International Symposium on High Performance Computer Architecture IEEE http://dblp.uni-trier.de/db/conf/hpca/ -
B FPGA ACM/SIGDA International Symposium on Field-Programmable Gate Arrays ACM http://dblp.uni-trier.de/db/conf/fpga/ A
B ICCAD International Conference on Computer-Aided Design IEEE/ACM http://dblp.uni-trier.de/db/conf/iccad/ A
B ICCD International Conference on Computer Design IEEE http://dblp.uni-trier.de/db/conf/iccd/ -
B DATE Design, Automation & Test in Europe IEEE/ACM http://dblp.uni-trier.de/db/conf/date/ A
B CODES+ISSS International Conference on Hardware/Software Co-design and System Synthesis ACM/IEEE https://dblp.uni-trier.de/db/conf/codesisss/index.html -
B HiPEAC International Conference on High Performance and Embedded Architectures and Compilers ACM http://dblp.uni-trier.de/db/conf/hipeac/ -
B HOT CHIPS Hot Chips: A Symposium on High Performance Chips IEEE https://dblp.org/db/conf/hotchips/index.html A
B CHES International Conference on Cryptographic Hardware and Embedded Systems IACR https://dblp.org/db/conf/ches/ A
C ASP-DAC Asia and South Pacific Design Automation Conference ACM/IEEE http://dblp.uni-trier.de/db/conf/aspdac A
C ISPD International Symposium on Physical Design ACM http://dblp.uni-trier.de/db/conf/ispd/ -
C GLSVLSI Great Lakes Symposium on VLSI ACM/IEEE http://dblp.uni-trier.de/db/conf/glvlsi/ -
C FPL International Conference on Field-Programmable Logic and Applications IEEE http://dblp.uni-trier.de/db/conf/fpl/ A
C FCCM IEEE Symposium on Field-Programmable Custom Computing Machines IEEE http://dblp.uni-trier.de/db/conf/fccm/ -
C FPT International Conference on Field-Programmable Technology IEEE http://dblp.uni-trier.de/db/conf/fpt/ A
C CASES International Conference on Compilers, Architectures, and Synthesis for Embedded Systems ACM http://dblp.uni-trier.de/db/conf/cases/index.html -
C ISLPED International Symposium on Low Power Electronics and Design ACM/IEEE http://dblp.uni-trier.de/db/conf/islped/ A
C HOTI IEEE Symposium on High-Performance Interconnects IEEE http://dblp.uni-trier.de/db/conf/hoti/ -
C ISCAS IEEE International Symposium on Circuits and Systems IEEE http://dblp.uni-trier.de/db/conf/iscas/ A

华中科技大学集成电路学院研究生毕业条件会议 (非CCF推荐)

毕业条件等级 会议简称 会议全称 出版社/主办
T2 IEDM IEEE International Electron Devices Meeting IEEE
T2 ISSCC IEEE International Solid-State Circuits Conference IEEE
T2 VLSI Symposia on Very Large Scale Integration Technology and Circuits IEEE
A ISPSD IEEE International Symposium on Power Semiconductor Devices and ICs IEEE
A IEEE MEMS IEEE International Conference on Micro Electro Mechanical Systems IEEE
A IEEE SENSORS IEEE Sensors Conference IEEE
A ICEPT International Conference on Electronic Packaging Technology IEEE
A IEEE IMS IEEE/MTT-S International Microwave Symposium IEEE
A ESSDERC European Solid-State Device Research Conference IEEE/ESSCIRC
A ESSCIRC European Solid-State Circuits Conference IEEE/ESSCIRC
A IMW IEEE International Memory Workshop IEEE
A APEC Applied Power Electronics Conference IEEE
A IECON Annual Conference of the IEEE Industrial Electronics Society IEEE
A RFIC IEEE Radio Frequency Integrated Circuits Symposium IEEE
A ICSICT IEEE International Conference on Solid-State and Integrated Circuit Technology IEEE
A IEEE EDSSC IEEE International Conference of Electron Devices and Solid-State Circuits IEEE
A TRANSDUCERS International Conference on Solid-State Sensors, Actuators and Microsystems IEEE
A EUROSENSORS Eurosensors Conference EUROSENSORS
A NEMS IEEE International Conference on Nano/Micro Engineered and Molecular Systems IEEE
A MWSCAS International Midwest Symposium on Circuits and Systems IEEE
A BioCAS IEEE Biomedical Circuits and Systems Conference IEEE
A IEEE APMC IEEE Asia-Pacific Microwave Conference IEEE
A IEEE IUS IEEE International Ultrasonics Symposium IEEE
A ASSCC Asian Solid-State Circuits Conference IEEE
A ACCS Asian Conference of Chemical Sensors ACCS
A ESSERC European Solid-State Electronics Research Conference IEEE
A CICC Custom Integrated Circuits Conference IEEE
A EPCOS European Phase Change and Ovonic Symposium EPCOS
A IMCS International Meeting on Chemical Sensors IMCS
A EDTM IEEE Electron Devices Technology and Manufacturing IEEE
A ICTA IEEE International Conference on Integrated Circuits, Technologies and Applications IEEE
A IEEE ICMMT IEEE International Conference on Microwave and Millimeter Waves IEEE
A ASICON IEEE International Conference on ASIC IEEE
A NVMTS Non-Volatile Memory Technology Symposium IEEE
A MEMRISIS International Conference on Memristive Materials, Devices & Systems MEMRISIS
A ICANS International Conference on Amorphous and Nano-crystalline Semiconductors ICANS
A APCAP Asia-Pacific Conference on Antenna and Propagation IEEE
A IWS International Wireless Symposium IEEE

中国计算机学会推荐国际学术期刊 (硬件设计相关)

CCF等级 会议简称 会议全称 出版社 网址 中科院分区
A TCAD IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE http://dblp.uni-trier.de/db/journals/tcad/ 计算机科学 3区
A TC IEEE Transactions on Computers IEEE http://dblp.uni-trier.de/db/journals/tc/index.html 计算机科学 2区
A TACO ACM Transactions on Architecture and Code Optimization ACM http://dblp.uni-trier.de/db/journals/taco/ 计算机科学 3区
B TODAES ACM Transactions on Design Automation of Electronic Systems ACM http://dblp.uni-trier.de/db/journals/todaes/ 计算机科学 4区
B TECS ACM Transactions on Embedded Computing Systems ACM http://dblp.uni-trier.de/db/journals/tecs/ 计算机科学 3区
B TRETS ACM Transactions on Reconfigurable Technology and Systems ACM http://dblp.uni-trier.de/db/journals/trets/ 计算机科学 3区 / 计算机：硬件 2区
B TVLSI IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE http://dblp.uni-trier.de/db/journals/tvlsi/ 工程技术 2区 / 计算机：硬件 2区
B JSA Journal of Systems Architecture: Embedded Software Design Elsevier http://dblp.uni-trier.de/db/journals/jsa/ 计算机科学 3区
C JETC ACM Journal on Emerging Technologies in Computing Systems ACM http://dblp.uni-trier.de/db/journals/jetc/ 计算机科学 4区
C Integration Integration, the VLSI Journal Elsevier http://dblp.uni-trier.de/db/journals/integration/ 工程技术 3区 / 计算机：硬件 4区
C JETTA Journal of Electronic Testing-Theory and Applications Springer https://dblp.org/db/journals/et/index.html 工程技术 4区
C MICPRO Microprocessors and Microsystems: Embedded Hardware Design Elsevier http://dblp.uni-trier.de/db/journals/mam/ 计算机科学 4区
C RTS Real-Time Systems Springer http://dblp.uni-trier.de/db/journals/rts/ 计算机科学 4区
C TJSC The Journal of Supercomputing Springer http://dblp.uni-trier.de/db/journals/tjs/ 计算机科学 4区
C TCASI IEEE Transactions on Circuits and Systems I: Regular Papers IEEE https://dblp.org/db/journals/tcasI/index.html 工程技术 2区

FPGA加速AI相关高质量论文收集

DAC 2025

Paper Title Authors
HiSpTRSV: Exploring Tile-Level Parallelism for SpTRSV Acceleration on FPGAs Fan Sun, Fang Dong, Dian Shen
NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI Hanchen Yang, Zishen Wan, Ritik Raj, Joongun Park, Ziwei Li, Ananda Samajdar, Arijit Raychowdhury, Tushar Krishna
FLAG: An FPGA-Based System for Low-Latency GNN Inference Service Using Vector Quantization Yunki Han, Taehwan Kim, Jiwan Kim, Seohye Ha, Lee-Sup Kim
XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification Shuai Zhou, Huinan Tian, Sisi Meng, Jianli Chen, Jun Yu, Kun Wang
AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs Jiawei Liang, Linfeng Du, Xiaofeng Zhou, Zhe Lin, Jiang Xu, Wei Zhang
DuoQ: A DSP Utilization-aware and Outlier-free Quantization for FPGA-based LLMs Acceleration Zhuoquan Yu, Huidong Ji, Yue Cao, Junfu Wu, Xiaoze Yan, Lirong Zheng, Zhuo Zou
MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models Shaoqiang Lu, Xuliang Yu, Tiandong Zhao, Siyuan Miao, Xinsong Sheng, Chen Wu, Liang Zhao, Ting-Jung Lin, Lei He
VersaSlot: Efficient Fine-grained FPGA Sharing with Big.Little Slots and Live Migration in FPGA Cluster Jianfeng Gu, Hao Wang, Xiaorang Guo, Martin Schulz, Michael Gerndt
FPGen-3D: Automated Framework for 3D-FPGA Architecture Generation and Exploration Ismael Youssef, Cong Callie Hao

DAC 2024

Paper Title Authors
PHD: Parallel Huffman Decoder on FPGA for Extreme Performance and Energy Efficiency Yunkun Liao, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan
Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model Zihao Chen, Jiangli Huang, Yiting Liu, Fan Yang, Li Shang, Dian Zhou, Xuan Zeng
SpectraFlux: Harnessing the Flow of Multi-FPGA in Mass Spectrometry Clustering Tianqi Zhang, Neha Prakriya, Sumukh Pinge, Jason Cong, Tajana Rosing
RL-PTQ: RL-based Mixed Precision Quantization for Hybrid Vision Transformers Eunji Kwon, Minxuan Zhou, Weihong Xu, Tajana Rosing, Seokhyeong Kang
Gypsophila: A Scalable and Bandwidth-Optimized Multi-Scalar Multiplication Architecture Changxu Liu, Hao Zhou, Lan Yang, Jiamin Xu, Patrick Dai, Fan Yang
SWAT: Scalable and Efficient Window Attention-based Transformers Acceleration on FPGAs Zhenyu Bai, Pranav Dangi, Huize Li, Tulika Mitra
CSTrans-OPU: An FPGA-based Overlay Processor with Full Compilation for Transformer Networks via Sparsity Exploration Yueyin Bai, Keqing Zhao, Yang Liu, Hongji Wang, Hao Zhou, Xiaoxing Wu, Jun Yu, Kun Wang
FLAME: Fully Leveraging MoE Sparsity for Transformer on FPGA Xuanda Lin, Huinan Tian, Wenxiao Xue, Lanqi Ma, Jialin Cao, Manting Zhang, Jun Yu, Kun Wang

DAC 2023

Paper Title Authors
Fast FPGA Accelerator of Graph Cut Algorithm with Out-of-order Parallel Execution in Folding Grid Architecture Guangyao Yan, Xinzhe Liu, Hui Wang, Yajun Ha
CHAM: A Customized Homomorphic Encryption Accelerator for Fast Matrix-Vector Product Xuanle Ren, Zhaohui Chen, Zhen Gu, Yanheng Lu, Ruiguang Zhong, Wen-Jie Lu, Jiansong Zhang, Yichi Zhang, Hanghang Wu, Xiaofu Zheng, Heng Liu, Tingqiang Chu, Cheng Hong, Changzheng Wei, Dimin Niu, Yuan Xie
Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications Jiaqi Yang, Hao Zheng, Ahmed Louri
FIONA: Fine-grained Incoherent Optical DNN Accelerator Search for Superior Efficiency and Robustness Mengquan Li, Kenli Li, Mingfeng Lan, Jie Xiong, Zhuo Tang, Weichen Liu
AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity Xiaolong Lin, Gang Li, Zizhao Liu, Yadong Liu, Fan Zhang, Zhuoran Song, Naifeng Jing, Xiaoyao Liang
HDSuper: Algorithm-Hardware Co-design for Light-weight High-quality Super-Resolution Accelerator Liang Chang, Xin Zhao, Dongqi Fan, Zhicheng Hu, Jun Zhou
EagleRec: Edge-Scale Recommendation System Acceleration with Inter-Stage Parallelism Optimization on GPUs Yongbo Yu, Fuxun Yu, Xiang Sheng, Chenchen Liu, Xiang Chen
PIM-HLS: An Automatic Hardware Generation Tool for Heterogeneous Processing-In-Memory-based Neural Network Accelerators Yu Zhu, Zhenhua Zhu, Guohao Dai, Fengbin Tu, Hanbo Sun, Kwang-Ting Cheng, Huazhong Yang, Yu Wang
Uint-Packing: Multiply Your DNN Accelerator Performance via Unsigned Integer DSP Packing Jingwei Zhang, Meng Zhang, Xinye Cao, Guoqing Li
PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table JaeHwa Jeon, Jae-Youn Hong, Sunghoon Kim, Insu Choi, Joon-Sung Yang

ICCAD 24

Title Authors
The Dawn of Domain-Specific Hardware System for Autonomous Machines Yuhao Zhu
Imaging, Computing, and Human Perception: Three Agents to Usher in the Autonomous Machine Computing Era Yuhao Zhu
Thinking and Moving: An Efficient Computing Approach for Integrated Task and Motion Planning in Cooperative Embodied AI Systems Zishen Wan, Yuhang Du, Mohamed Ibrahim, Yang (Katie) Zhao, Tushar Krishna, Arijit Raychowdhury
Generative AI Agents in Autonomous Machines: A Safety Perspective Jason Jabbour, Vijay Janapa Reddi
Dataflow Accelerator Architecture for Autonomous Machine Computing Shaoshan Liu, Yuhao Zhu, Bo Yu, Jean-Luc Gaudiot, Guangrong Gao
LLM4HWDesign Contest: Constructing a Comprehensive Dataset for LLM-Assisted Hardware Code Generation Zhongzhi Yu, Chaojian Li, Yongan Zhang, Mingjie Liu, Nathaniel Ross Pinckney, Wenfei Zhou, Haoyu Yang, Rongjian Liang, Haoxing Ren, Yingyan Celine Lin

ICCAD 23

Title Authors
CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization Rongjian Liang, Anthony Agnesina, Geraldo Pradipta, Vidya A. Chhabria, Haoxing Ren
FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow Thilini Kaushalya Bandara, Dan Wu, Rohan Juneja, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh
Bespoke Approximation of Multiplication-Accumulation and Activation Targeting Printed Multilayer Perceptrons Florentia Afentaki, Gurol Saglam, Argyris Kokkinis, Kostas Siozios, Georgios Zervakis, Mehdi B. Tahoori
Side Channel-Assisted Inference Attacks on Machine Learning-Based ECG Classification Jialin Liu, Houman Homayoun, Chongzhou Fang, Ning Miao, Han Wang
Path-Based Processing using In-Memory Systolic Arrays for Accelerating Data-Intensive Applications Muhammad Rashedul Haq Rashed, Sven Thijssen, Sumit Kumar Jha, Hao Zheng, Rickard Ewetz
Routability Prediction and Optimization Using Explainable AI Seonghyeon Park, Daeyeon Kim, Seongbin Kwon, Seokhyeong Kang
TRAIN: A Reinforcement Learning Based Timing-Aware Neural Inference on Intermittent Systems Shu-Ting Cheng, Wen Sheng Lim, Chia-Heng Tu, Yuan-Hao Chang
PRIMO: A Full-Stack Processing-in-DRAM Emulation Framework for Machine Learning Workloads Jaehoon Heo, Yongwon Shin, Sangjin Choi, Sungwoong Yune, Jung-Hoon Kim, Hyojin Sung, Youngjin Kwon, Joo-Young Kim
BOOST: Block Minifloat-Based On-Device CNN Training Accelerator with Transfer Learning Chuliang Guo, Binglei Lou, Xueyuan Liu, David Boland, Philip H. W. Leong, Cheng Zhuo
INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation Processing Stefan Abi-Karam, Rishov Sarkar, Dejia Xu, Zhiwen Fan, Zhangyang Wang, Cong Hao
Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-Level Sparsity via Mixture-of-Experts Rishov Sarkar, Hanxue Liang, Zhiwen Fan, Zhangyang Wang, Cong Hao
Fast and Fair Medical AI on the Edge Through Neural Architecture Search for Hybrid Vision Models Changdi Yang, Yi Sheng, Peiyan Dong, Zhenglun Kong, Yanyu Li, Pinrui Yu, Lei Yang, Xue Lin, Yanzhi Wang

FPGA 25

Title Authors
FlightVGM: Efficient Video Generation Model Inference with Online Sparsification and Hybrid Precision on FPGAs Jun Liu, Shulin Zeng, Li Ding, Widyadewi Soedarmadji, Hao Zhou, Zehao Wang, Jinhao Li, Jintao Li, Yadong Dai, Kairui Wen, Shan He, Yaqi Sun, Yu Wang, Guohao Dai
TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Trees Alireza Khataei, Kia Bazargan
Greater than the Sum of its LUTs: Scaling Up LUT-based Neural Networks with AmigoLUT Olivia Weng, Marta Andronic, Danial Zuberi, Jiaqing Chen, Caleb Geniesse, George A. Constantinides, Nhan Tran, Nicholas J. Fraser, Javier Mauricio Duarte, Ryan Kastner
ReducedLUT: Table Decomposition with "Don't Care" Conditions Oliver Cassidy, Marta Andronic, Samuel Coward, George A. Constantinides
InTRRA: Inter-Task Resource-Repurposing Accelerator for Efficient Transformer Inference on FPGAs Zifan He, Hersh Gupta, Huifeng Ke, Jason Cong
DPUV4E: High-Throughput DPU Architecture Design for CNN on Versal ACAP Guoyu Li, Pengbo Zheng, Jian Weng, Enshan Yang
HiGTR: High-Performance FPGA Implementation of Complete GNN-based Trajectory Reconstruction for HEP Yun-Chen Yang, Hsuan-Wei Yu, Bo-Cheng Lai, Shih-Chieh Hsu, Mark S. Neubauer, Santosh Parajuli
FMC-LLM: Enabling FPGAs for Efficient Batched Decoding of 70B+ LLMs with a Memory-Centric Streaming Architecture Wenheng Ma, Xinhao Yang, Shulin Zeng, Tengxuan Liu, Libo Shen, Hongyi Wang, Shiyao Li, Jiewen Wang, Yuhan Zhang, Hao Guo, Jintao Li, Ziming Zhang, Zhenhua Zhu, Xuefei Ning, Tsung-Yi Ho, Guohao Dai, Yu Wang

FPGA 24

Title Authors
SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration Jinming Zhuang, Zhuoping Yang, Shixin Ji, Heng Huang, Alex K. Jones, Jingtong Hu, Yiyu Shi, Peipei Zhou
LevelST: Stream-based Accelerator for Sparse Triangular Solver Zifan He, Linghao Song, Robert F. Lucas, Jason Cong
HiSpMV: Hybrid Row Distribution and Vector Buffering for Imbalanced SpMV Acceleration on FPGAs Manoj B. Rajashekar, Xingyu Tian, Zhenman Fang
A Flexible, Fast, Low Bandwidth Block-based Acceleration Architecture for CNN Inference on FPGAs Yan Chen, Kiyofumi Tanaka

FPGA 23

Title Authors
AoCStream: All-on-Chip CNN Accelerator With Stream-Based Line-Buffer Architecture Hyeong-Ju Kang
Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural Networks Ruiqi Chen, Haoyang Zhang, Yuhanxiao Ma, Enhao Tang, Shun Li, Yanxiang Zhu, Jun Yu, Kun Wang
Single-Batch CNN Training using Block Minifloats on FPGAs Chuliang Guo, Binglei Lou, Xueyuan Liu, David Boland, Philip H. W. Leong
FNNG: A High-Performance FPGA-based Accelerator for K-Nearest Neighbor Graph Construction Chaoqiang Liu, Haifeng Liu, Long Zheng, Yu Huang, Xiangyu Ye, Xiaofei Liao, Hai Jin
ACTS: A Near-Memory FPGA Graph Processing Framework Wole Jaiyeoba, Nima Elyasi, Changho Choi, Kevin Skadron
Exploring the Versal AI Engines for Accelerating Stencil-based Atmospheric Advection Simulation Nick Brown

TCAS-I 25

Title Author(s)
A 701.7 TOPS/W Compute-in-Memory Processor With Time-Domain Computing for Spiking Neural Network Keonhee Park, Hoichang Jeong, Seungbin Kim, Jeongmin Shin, Minseo Kim, Kyuho Jason Lee
HRCIM-NTT: An Efficient Compute-in-Memory NTT Accelerator With Hybrid-Redundant Numbers Xu Zhang, Yaodong Wei, Minghao Li, Jing Tian, Zhongfeng Wang
A 3-D Multi-Precision Scalable Systolic FMA Architecture Haotian Liu, Xicheng Lu, Xiaoyu Yu, Kai Li, Kaiyuan Yang, Haihang Xia, Sizhao Li, Tiantai Deng
A-Connect: An Ex Situ Training Methodology to Mitigate Stochasticity in Neural Network Analog Accelerators Luis E. Rueda G., Ricardo Vergel, Edward Silva, Elkim Roa
Differentiable Cost Model for Neural-Network Accelerator Regarding Memory Hierarchy Joschua Conrad, Simon Wilhelmstätter, Rohan Asthana, Vasileios Belagiannis, Maurits Ortmanns
Efficient Integer-Only-Inference of Gradient Boosting Decision Trees on Low-Power Devices Majed Alsharari, Son T. Mai, Roger F. Woods, Carlos Reaño

TCAS-I 24

Title Author(s)
MERRC: A Memristor-Enabled Reconfigurable Low-Power Reservoir Computing Architecture at the Edge Fabiha Nowshin, Yi Huang, Md. Rubel Sarkar, Qiangfei Xia, Yang Yi
CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices Yongliang Zhou, Zixuan Zhou, Yiming Wei, Zhen Yang, Xiao Lin, Chenghu Dai, Licai Hao, Chunyu Peng, Hao Cai, Xiulong Wu
NASA-F: FPGA-Oriented Search and Acceleration for Multiplication-Reduced Hybrid Networks Huihong Shi, Yang Xu, Yuefei Wang, Wendong Mao, Zhongfeng Wang
Energy-Efficient BNN Accelerator With Two-Stage Value Prediction for Sparse-Edge Gesture Recognition Yongliang Zhang, Yitong Rong, Xuyang Duan, Zhen Yang, Qiang Li, Ziyu Guo, Xu Cheng, Xiaoyang Zeng, Jun Han
Full-Analog Reservoir Computing Circuit Based on Memristor With a Hybrid Wide-Deep Architecture Liangyu Chen, Xiaoping Wang, Chao Yang, Zhanfei Chen, Junming Zhang, Zhigang Zeng
Energy Efficient All-Digital Time-Domain Compute-in-Memory Macro Optimized for Binary Neural Networks Jie Lou, Florian Freye, Christian Lanius, Tobias Gemmeke

TCAS-I 23

Title Author(s)
Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators Hendrik Wöhrle, Felix Schneider, Fabian Schlenke, Denis Lebold, Mariela De Lucas Alvarez, Frank Kirchner, Michael Karagounis
Process, Bias, and Temperature Scalable CMOS Analog Computing Circuits for Machine Learning Pratik Kumar, Ankita Nandi, Shantanu Chakrabartty, Chetan Singh Thakur
SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization Yiqi Wang, Fengbin Tu, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
FPGA-Oriented Search and Acceleration for Multiplication-Reduced Hybrid Networks Huihong Shi, Yang Xu, Yuefei Wang, Wendong Mao, Zhongfeng Wang
Accelerating Deep Convolutional Neural Networks Using Number Theoretic Transform Prasetiyo, Seongmin Hong, Yashael Faith Arthanto, Joo-Young Kim
ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays Hongwu Jiang, Shanshi Huang, Wantong Li, Shimeng Yu
ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Xiaoyong Xue, Xiaoyang Zeng

TCAD 25

Title Author(s)
Deep Investigation on Stealthy DVFS Fault Injection Attacks at DNN Hardware Accelerators Junge Xu, Fan Zhang, Wenguang Jin, Kun Yang, Zeke Wang, Weixiong Jiang, Yajun Ha
LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator Tianyang Yu, Bi Wu, Ke Chen, Gong Zhang, Weiqiang Liu
Fast-OverlaPIM: A Fast Overlap-Driven Mapping Framework for Processing In-Memory Neural Network Acceleration Xuan Wang, Minxuan Zhou, Tajana Rosing
PEPPR-DWS on FPGA: Elevating Universal Parallelism and Precision Through Pulse-Enhanced Push-Relabel and Diffusion Wave Search Zehua Dong, Boyu Zhang, Yucheng Jiang, Yu Yu, Han Li, Songping Mai
DiMO-CNN: Deep Learning Toolkit-Accelerated Analytical Modeling and Optimization of CNN Hardware and Dataflow Jianfeng Song, Rongjian Liang, Bo Yuan, Jiang Hu
CyberRL: Brain-Inspired Reinforcement Learning for Efficient Network Intrusion Detection Mariam Issa, Hanning Chen, Junyao Wang, Mohsen Imani
DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA Kui Dai, Zheren Xie, Shuanglong Liu
Highly Parallel CNN Accelerator for RepVGG-Like Network Training on FPGAs Chuliang Guo, Binglei Lou, David Boland, Philip H. W. Leong
Light-CIM: A Lightweight ADC/DAC-Fewer RRAM CIM DNN Accelerator Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Xiaoyong Xue, Xiaoyang Zeng
DSAV: A Deep Sparse Acceleration Framework for Voxel-Based 3-D Object Detection Haining Fang, Yujuan Tan, Ao Ren, Wei Zhuang, Yang Hua, ZhiYong Qin, Duo Liu

TCAD 24

Title Author(s)
PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators Arman Roohi, Sepehr Tabrizchi, Mehrdad Morsali, David Z. Pan, Shaahin Angizi
CIMQ: A Hardware-Efficient Quantization Framework for Computing-In-Memory-Based Neural Network Accelerators Jinyu Bai, Sifan Sun, Weisheng Zhao, Wang Kang
DiagNNose: Toward Error Localization in Deep Learning Hardware-Based on VTA-TVM Stack Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu
Automated Optical Accelerator Search Toward Superior Acceleration Efficiency, Inference Robustness, and Development Speed Mengquan Li, Kenli Li, Chao Wu, Gang Liu, Mingfeng Lan, Yunchuan Qin, Zhuo Tang, Weichen Liu
Precision-Scalable Deep Neural Network Accelerator With Activation Sparsity Exploitation Wenjie Li, Aokun Hu, Ningyi Xu, Guanghui He
Efficient N:M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design Chao Fang, Wei Sun, Aojun Zhou, Zhongfeng Wang
GTCO: Graph and Tensor Co-Design for Transformer-Based Image Recognition on Tensor Cores Yang Bai, Xufeng Yao, Qi Sun, Wenqian Zhao, Shixin Chen, Zixiao Wang, Bei Yu

TCAD 23

Title Author(s)
SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration Fengbin Tu, Yiqi Wang, Ling Liang, Yufei Ding, Leibo Liu, Shaojun Wei, Shouyi Yin, Yuan Xie
Energon: Toward Efficient Acceleration of Transformers Using Dynamic Sparse Attention Zhe Zhou, Junlin Liu, Zhenyu Gu, Guangyu Sun
PASGCN: A ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs Tao Yang, Dongyue Li, Fei Ma, Zhuoran Song, Yilong Zhao, Jiaxi Zhang, Fangxin Liu, Li Jiang
SoBS-X: Squeeze-Out Bit Sparsity for ReRAM-Crossbar-Based Neural Network Accelerator Fangxin Liu, Zongwu Wang, Yongbiao Chen, Zhezhi He, Tao Yang, Xiaoyao Liang, Li Jiang
Quantized Neural Network Synthesis for Direct Logic Circuit Implementation Yu-Shan Huang, Jie-Hong R. Jiang, Alan Mishchenko
DTATrans: Leveraging Dynamic Token-Based Quantization With Accuracy Compensation Mechanism for Efficient Transformer Architecture Tao Yang, Fei Ma, Xiaoling Li, Fangxin Liu, Yilong Zhao, Zhezhi He, Li Jiang
Offline Training-Based Mitigation of IR Drop for ReRAM-Based Deep Neural Network Accelerators Sugil Lee, Mohammed E. Fouda, Jongeun Lee, Ahmed M. Elt

FPGA加速密码相关高质量论文收集

DAC 2025

Titles Authors
FPGA-TrustZone: Security Extension of TrustZone to FPGA for SoC-FPGA Heterogeneous Architecture S. Wang; X. Fan; X. Xu; S. Wang; L. Ju; Z. Zhou
AmpereBleed: Exploiting On-chip Current Sensors for Circuit-Free Attacks on ARM-FPGA SoCs X. Zhang; Y. Yang; J. Zou; Q. Shen; Z. Zhang; Y. Gao; Z. Wu; T. E. Carlson

DAC 2024

Paper Title Authors
MSMAC: Accelerating Multi-Scalar Multiplication for Zero-Knowledge Proof Pengcheng Qiu, Guiming Wu, Tingqiang Chu, Changzheng Wei, Runzhou Luo, Ying Yan, Wei Wang, Hui Zhang
Gypsophila: A Scalable and Bandwidth-Optimized Multi-Scalar Multiplication Architecture Changxu Liu, Hao Zhou, Lan Yang, Jiamin Xu, Patrick Dai, Fan Yang
Order-Preserving Cryptography for the Confidential Inference in Random Forests: FPGA Design and Implementation Rupesh Raj Karn, Kashif Nawaz, Ibrahim Abe M. Elfadel
DH-TRNG: A Dynamic Hybrid TRNG with Ultra-High Throughput and Area-Energy Efficiency Yuan Zhang, Kuncai Zhong, Jiliang Zhang
NTT/INTT Accelerator with Ultra-High Throughput and Area Efficiency for FHE Zhaojun Lu, Weizong Yu, Peng Xu, Wei Wang, Jiliang Zhang, Dengguo Feng
Chiplever: Towards Effortless Extension of Chiplet-based System for FHE Yibo Du, Ying Wang, Bing Li, Fuping Li, Shengwen Liang, Huawei Li, Xiaowei Li, Yinhe Han
FHE-CGRA: Enable Efficient Acceleration of Fully Homomorphic Encryption on CGRAs Miaomiao Jiang, Yilan Zhu, Honghui You, Cheng Tan, Zhaoying Li, Jiming Xu, Lei Ju

DAC 2023

Titles Authors
An FPGA-Compatible TRNG with Ultra-High Throughput and Energy Efficiency Z. Lu; H. Qidiao; Q. Chen; Z. Liu; J. Zhang
Mckeycutter: A High-throughput Key Generator of Classic McEliece on Hardware Y. Zhu; W. Zhu; C. Chen; M. Zhu; Z. Li; S. Wei; L. Liu
CHAM: A Customized Homomorphic Encryption Accelerator for Fast Matrix-Vector Product X. Ren; Z. Chen; Z. Gu; Y. Lu; R. Zhong; W.-J. Lu; J. Zhang; Y. Zhang; H. Wu; X. Zheng; H. Liu; T. Chu; C. Hong; C. Wei; D. Niu; Y. Xie
PASNet: Polynomial Architecture Search Framework for Two-party Computation-based Secure Neural Network Deployment H. Peng; S. Zhou; Y. Luo; N. Xu; S. Duan; R. Ran; J. Zhao; C. Wang; T. Geng; W. Wen; X. Xu; C. Ding

ICCAD 24

Title Authors
Enhancing Privacy-Preserving Computing with Optimized CKKS Encryption: A Hardware Acceleration Approach Tianyou Bao et al.
OpenNTT - An Automated Toolchain for Compiling High-Performance NTT Accelerators in FHE Florian Krieger et al.

ICCAD 23

Title Authors
KyberMat: Efficient Accelerator for Matrix-Vector Polynomial Multiplication in CRYSTALS-Kyber Scheme via NTT and Polyphase Decomposition Weihang Tan, Yingjie Lao, Keshab K. Parhi
Invited Paper: Dilithium Hardware-Accelerated Application Using OpenCL-Based High-Level Synthesis Alexander El-Kady, Apostolos P. Fournaris, Vassilis Paliouras
Machine Learning Vulnerability Assessment of Ring Oscillator Physical Unclonable Functions H. Kareem; D. Dunaev

FPGA 25

Title Authors
FAST: FPGA Acceleration of Fully Homomorphic Encryption with Efficient Bootstrapping Zhihan Xu, Tian Ye, Rajgopal Kannan, Viktor K. Prasanna
OLA: An FPGA-based Overlay Accelerator for Privacy Preserving Machine Learning with Homomorphic Encryption Yang Yang, Rajgopal Kannan, Viktor K. Prasanna
CIVIC-FPGA: A Trusted FPGA Design Validation by Multi-Tenant Cloud Providers Yu Feng, Zhaoqi Wang, Christophe Bobda
HEDWIG: Homomorphic Encryption Accelerator Design Using BFV-HPS With HiGh-Speed Fixed-Point Approximation Antian Wang, Weihang Tan, Zhenyu Xu, Tao Wei, Caiwen Ding, Keshab K. Parhi, Yingjie Lao
RRNS Arith Lib - An Open-Source Redundant Residue Number System Arithmetic VHDL Library Tim Oberschulte, Enno Sievers, Holger Blume

FPGA 24

Title Authors
Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar Multiplication Engine Andy Ray, Benjamin Devlin, Fu Yong Quah, Rahul Yesantharao
ISO-TENANT: Rethinking FPGA Power Distribution Network (PDN): A Hardware Based Solution for Remote Power Side Channel Attacks in FPGA Muhammed Kawser Ahmed, Christophe Bobda
Covert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs via Covert Channels Hassan Nassar, Philipp Machauer, Dennis R. E. Gnad, Lars Bauer, Mehdi B. Tahoori, Jörg Henkel

FPGA 23

Title Authors
Cyclone-NTT: An NTT/FFT Architecture Using Quasi-Streaming of Large Datasets on DDR- and HBM-based FPGA Platforms Kaveh Aasaraai, Emanuele Cesena, Rahul Maganti, Nicolas Stalder, Javier Varela, Kevin Bowers
Power Side-channel Countermeasures for ARX Ciphers using High-level Synthesis Saya Inagaki, Mingyu Yang, Yang Li, Kazuo Sakiyama, Yuko Hara-Azumi
CSAIL2019 Crypto-Puzzle Solver Architecture Sergey Gribok, Bogdan Pasca, Martin Langhammer

HPCA 2025

Title Authors
Hydra: Scale-out FHE Accelerator Architecture for Secure Deep Learning on FPGA Yinghao Yang, Xicheng Xu, Haibin Zhang, Jie Song, Xin Tang, Hang Lu, Xiaowei Li
FHENDI: A Near-DRAM Accelerator for Compiler-Generated Fully Homomorphic Encryption Applications Yongmo Park, Aporva Amarnath, Subhankar Pal, Karthik Swaminathan, Alper Buyuktosunoglu, Hayim Shaul, Ehud Aharoni, Nir Drucker, Wei D. Lu, Omri Soceanu, Pradip Bose
EFFACT: A Highly Efficient Full-Stack FHE Acceleration Platform Yi Huang, Xinsheng Gong, Xiangyu Kong, Dibei Chen, Jianfeng Zhu, Wenping Zhu, Liangwei Li, Mingyu Gao, Shaojun Wei, Aoyang Zhang, Leibo Liu

HPCA 2024

Title Authors
Morphling: A Throughput-Maximized TFHE-based Accelerator using Transform-domain Reuse Prasetiyo, Adiwena Putra, Joo-Young Kim:

HPCA 2023

Title Authors
FAB: An FPGA-based Accelerator for Bootstrappable Fully Homomorphic Encryption Rashmi Agrawal, Leo de Castro, Guowei Yang, Chiraag Juvekar, Rabia Tugce Yazicigil, Anantha P. Chandrakasan, Vinod Vaikuntanathan, Ajay Joshi
FxHENN: FPGA-based acceleration framework for homomorphic encrypted CNN inference Yilan Zhu, Xinyao Wang, Lei Ju, Shanqing Guo

ISCA 2025

Title Authors
Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design Tianwei Pan, Tianao Dai, Jianlei Yang, Hongbin Jing, Yang Su, Zeyu Hao, Xiaotao Jia, Chunming Hu, Weisheng Zhao
FAST: An FHE Accelerator for Scalable-parallelism with Tunable-bit Shengyu Fan, Xianglong Deng, Liang Kong, Guiming Shi, Guang Fan, Dan Meng, Rui Hou, Mingzhe Zhang

ISCA 2024

Title Authors
HEAP: A Fully Homomorphic Encryption Accelerator with Parallelized Bootstrapping Rashmi S. Agrawal, Anantha P. Chandrakasan, Ajay Joshi

ISCA 2023

Title Authors
F4T: A Fast and Flexible FPGA-based Full-stack TCP Acceleration Framework Junehyuk Boo, Yujin Chung, Eunjin Baek, Seongmin Na, Changsu Kim, Jangwoo Kim
HAAC: A Hardware-Software Co-Design to Accelerate Garbled Circuits Jianqiao Mo, Jayanth Gopinath, Brandon Reagen
SHARP: A Short-Word Hierarchical Accelerator for Robust and Practical Fully Homomorphic Encryption Jongmin Kim, Sangpyo Kim, Jaewan Choi, Jaiyoung Park, Donghwan Kim, Jung Ho Ahn

MICRO 2024

Title Authors
Trinity: A General Purpose FHE Accelerator Xianglong Deng, Shengyu Fan, Zhicheng Hu, Zhuoyu Tian, Zihao Yang, Jiangrui Yu, Dingyuan Cao, Dan Meng, Rui Hou, Meng Li, Qian Lou, Mingzhe Zhang
UFC: A Unified Accelerator for Fully Homomorphic Encryption Minxuan Zhou, Yujin Nam, Xuan Wang, Youhak Lee, Chris Wilkerson, Raghavan Kumar, Sachin Taneja, Sanu Mathew, Rosario Cammarota, Tajana Rosing
A Scalable, Efficient, and Robust Dynamic Memory Management Library for HLS-based FPGAs Qinggang Wang, Long Zheng, Zhaozeng An, Shuyi Xiong, Runze Wang, Yu Huang, Pengcheng Yao, Xiaofei Liao, Hai Jin, Jingling Xue
Accelerating Zero-Knowledge Proofs Through Hardware-Algorithm Co-Design Nikola Samardzic, Simon Langowski, Srinivas Devadas, Daniel Sánchez

MICRO 2023

Title Authors
Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping Adiwena Putra, Prasetiyo, Yi Chen, John Kim, Joo-Young Kim
MAD: Memory-Aware Design Techniques for Accelerating Fully Homomorphic Encryption Rashmi Agrawal, Leo de Castro, Chiraag Juvekar, Anantha P. Chandrakasan, Vinod Vaikuntanathan, Ajay Joshi

ASPLOS

偏重方法，策略等方面，不偏重实现

TCAS-I 25

Title Author(s)
Memristive Tabu Learning Neuron Generated Multi-Wing Attractor With FPGA Implementation and Application in Encryption Zhiqiang Wei, Yuxiang Zhang, et al.
Configurable Cascaded Carry Chains for High Reliability TERO PUFs on FPGAs Yifan Chen, Xiaoxiao Wang, et al.

TCAS-I 24

Title Author(s)
High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Yusuke Ito, Naofumi Homma, et al.

TCAS-I 23

Title Author(s)
High-Speed FPGA-Based Hardware Implementation for Leighton-Micali Signature Yuta Watanabe, Naofumi Homma, et al.

tcad 44

title author
PEPPR-DWS on FPGA: Elevating Universal Parallelism and Precision Through Pulse-Enhanced Push-Relabel and Diffusion Wave Search Zehua Dong, Boyu Zhang, Yucheng Jiang, Yu Yu, Han Li, Songping Mai
Fast Acceleration Strategies for XOR-Based Erasure Codes Wei Wang, Min Lyu, Tianyang Niu, Qiliang Li, Liangliang Xu, Yinlong Xu
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy Rui Li, Lin Li, Heng Yu, Masahiro Fujita, Weixiong Jiang, Yajun Ha
Algorithmically Enhanced Design of Spintronic-Based Tunable True Random Number Generator for Dependable Stochastic Computing Amir Bahador, Mohammad Hossein Moaiyeri, Reza Ghaderi
A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections Xun Jiang, Jiarui Wang, Jing Mai, Zhixiong Di, Yibo Lin

tcad 43

title author
H2B: Crypto Hash Functions Based on Hybrid Ring Generators Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
A High-Performance, Conflict-Free Memory-Access Architecture for Modular Polynomial Multiplication Zeming Cheng, Bo Zhang, Massoud Pedram
Compact Instruction Set Extensions for Kyber Lu Li, Guofeng Qin, Yang Yu, Weijia Wang
ISA Extensions of Shuffling Against Side-Channel Attacks Jiayun Zhou, Guofeng Qin, Lu Li, Chun Guo, Weijia Wang
Hardware Constructions for Error Detection in WG-29 Stream Cipher Benchmarked on FPGA Jasmin Kaur, Alvaro Cintas Canto, Mehran Mozaffari Kermani, Reza Azarderakhsh

tcad 42

title author
Low-Cost Shuffling Countermeasures Against Side-Channel Attacks for NTT-Based Post-Quantum Cryptography Zhaohui Chen, Yuan Ma, Jiwu Jing
Algorithmic Obfuscation for LDPC Decoders Jingbo Zhou, Xinmiao Zhang
Fuzzing+Hardware Performance Counters-Based Detection of Algorithm Subversion Attacks on Postquantum Signature Schemes Animesh Basak Chowdhury, Anushree Mahapatra, Deepraj Soni, Ramesh Karri
Learning Malicious Circuits in FPGA Bitstreams Rana Elnaggar, Jayeeta Chaudhuri, Ramesh Karri, Krishnendu Chakrabarty
SeqL+: Secure Scan-Obfuscation With Theoretical and Empirical Validation Seetal Potluri, Shamik Kundu, Akash Kumar, Kanad Basu, Aydin Aysu
New Approaches of Side-Channel Attacks Based on Chip Testing Methods Sergej Meschkov, Dennis R. E. Gnad, Jonas Krautter, Mehdi B. Tahoori
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation Jianan Mu, Yi Ren, Wen Wang, Yizhong Hu, Shuai Chen, Chip-Hong Chang, Junfeng Fan, Jing Ye, Yuan Cao, Huawei Li, Xiaowei Li
posted @ 2025-11-08 18:35  Wunyje  阅读(21)  评论(0)    收藏  举报