基于Verilog的串口发送程序
一、模块框图及基本思路
tx_bps_module:波特率时钟产生模块
tx_control_module:串口发送的核心控制模块
tx_module:前两个模块的组合
control_module:发送控制模块，每秒触发一次发送
tx_top_module:tx_module+control_module
二、软件部分
tx_bps_module:
1 module tx_bps_module #(parameter Baud=9600)( 2 CLK,RSTn, 3 Count_Sig, 4 BPS_CLK 5 ); 6 input CLK; 7 input RSTn; 8 input Count_Sig; 9 output BPS_CLK; 10 11 /***************************/ 12 localparam Baud_Div=50_000_000/Baud-1; 13 localparam Baud_Div2=Baud_Div/2; 14 15 reg[15:0] Count_BPS; 16 /*************************/ 17 always @(posedge CLK or negedge RSTn) 18 begin 19 if(!RSTn) 20 Count_BPS<=16'd0; 21 else if(Count_BPS==Baud_Div) 22 Count_BPS<=16'd0; 23 else if(Count_Sig) 24 Count_BPS<=Count_BPS+1; 25 else Count_BPS<=16'd0; 26 end 27 /************************/ 28 assign BPS_CLK=(Count_BPS==Baud_Div2)?1'b1:1'b0; 29 endmodule
tx_control_module:
1 module tx_control_module( 2 CLK,RSTn, 3 TX_En_Sig,TX_Data,BPS_CLK, 4 TX_Done_Sig,TX_Pin_Out 5 ); 6 input CLK,RSTn; 7 input TX_En_Sig,BPS_CLK; 8 input [7:0]TX_Data; 9 output TX_Done_Sig,TX_Pin_Out; 10 /***************************************/ 11 reg rTX; 12 reg isDone; 13 reg[3:0] i; 14 always @(posedge CLK or negedge RSTn) 15 begin 16 if(!RSTn) 17 begin 18 rTX<=1'b1; 19 isDone<=1'b0; 20 i<=4'd0; 21 end 22 else if(TX_En_Sig) 23 begin 24 case(i) 25 4'd0:if(BPS_CLK) begin rTX<=0;i<=i+1'b1; end 26 4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8: 27 if(BPS_CLK) begin rTX<=TX_Data[i-1];i<=i+1'b1; end 28 4'd9:if(BPS_CLK) begin rTX<=1;i<=i+1'b1; end 29 4'd10:if(BPS_CLK) begin rTX<=1;i<=i+1'b1; end 30 4'd11:if(BPS_CLK) begin isDone<=1;i<=i+1'b1; end 31 4'd12: begin isDone<=0;i<=1'b0; end 32 endcase 33 end 34 end 35 /***************************************/ 36 assign TX_Pin_Out=rTX; 37 assign TX_Done_Sig=isDone; 38 endmodule
tx_module:
1 module tx_module( 2 CLK,RSTn, 3 TX_En_Sig,TX_Data,TX_Pin_Out,TX_Done_Sig 4 ); 5 input CLK; 6 input RSTn; 7 input TX_En_Sig; 8 input [7:0] TX_Data; 9 output TX_Pin_Out; 10 output TX_Done_Sig; 11 12 wire BPS_CLK; 13 14 tx_bps_module U0(.CLK(CLK),.RSTn(RSTn),.Count_Sig(TX_En_Sig),.BPS_CLK(BPS_CLK)); 15 tx_control_module U1(.CLK(CLK),.RSTn(RSTn),.TX_En_Sig(TX_En_Sig), 16 .BPS_CLK(BPS_CLK),.TX_Data(TX_Data),.TX_Done_Sig(TX_Done_Sig), 17 .TX_Pin_Out(TX_Pin_Out)); 18 endmodule
control_module:
1 module control_module( 2 CLK, RSTn, 3 TX_Done_Sig, 4 TX_En_Sig, TX_Data 5 ); 6 input CLK; 7 input RSTn; 8 input TX_Done_Sig; 9 output TX_En_Sig; 10 output [7:0]TX_Data; 11 12 /***********************************************/ 13 localparam T1S=26'd49_999_99; 14 reg [25:0] Count_Sec; 15 always @(posedge CLK or negedge RSTn) 16 begin 17 if(!RSTn) 18 Count_Sec<=26'd0; 19 else if(Count_Sec==T1S) Count_Sec<=26'd0; 20 else Count_Sec<=Count_Sec+1'b1; 21 end 22 /************************************************/ 23 24 reg[7:0] rData; 25 reg isEn; 26 always @(posedge CLK or negedge RSTn) 27 begin 28 if(!RSTn) 29 begin 30 rData<=8'h31; 31 isEn<=1'b0; 32 end 33 else if(TX_Done_Sig) 34 begin 35 rData<=8'h31; 36 isEn<=1'b0; 37 end 38 else if(Count_Sec==T1S) isEn<=1'b1; 39 end 40 41 /*************************************************/ 42 assign TX_Data=rData; 43 assign TX_En_Sig=isEn; 44 45 /*************************************************/ 46 endmodule
tx_top_module:
1 module tx_top_module( 2 CLK,RSTn, 3 TX_Pin_Out 4 ); 5 input CLK; 6 input RSTn; 7 output TX_Pin_Out; 8 9 wire TX_Done_Sig; 10 wire TX_En_Sig; 11 wire [7:0]TX_Data; 12 control_module U0( 13 .CLK(CLK), .RSTn(RSTn), 14 .TX_Done_Sig(TX_Done_Sig), 15 .TX_En_Sig(TX_En_Sig), .TX_Data(TX_Data)); 16 17 tx_module U1( 18 .CLK(CLK),.RSTn(RSTn), 19 .TX_En_Sig(TX_En_Sig),.TX_Data(TX_Data),.TX_Pin_Out(TX_Pin_Out),.TX_Done_Sig(TX_Done_Sig) 20 ); 21 endmodule
三、硬件部分
黑金SPARTAN开发板
1 NET "CLK" LOC = T8; 2 NET "RSTn" LOC = L3; 3 NET "TX_Pin_Out" LOC = D12;
