状态机-阶段1 练习4

 

 

注意：dout 在dout_vld有效时，其值有效，说明 dou_vld 和 dout 是在同一拍上

 

 状态机：

 

产生输出：

代码：

module state_test(
                    clk,
                    rst_n,
                    din_vld,
                    din,
                    
                    dout_vld,
                    dout
);

parameter        S0 = 0;
parameter        S1 = 1;
parameter        S2 = 2;
parameter        S3 = 3;
parameter        S4 = 4;

input            clk;
input             rst_n;
input            din_vld;
input[2-1:0]    din;

output            dout_vld;
output[6-1:0]    dout;


wire              S02S1_start;
wire              S02S2_start;
wire              S12S2_start;
wire              S12S3_start;
wire              S12S0_start;
wire              S22S3_start;
wire              S22S4_start;
wire              S22S0_start;
wire              S32S4_start;
wire              S32S0_start;
wire              S42S0_start;
wire            vld0;
wire            vld1;
wire            vld2;
wire            vld3;
wire            vld4;


reg                dout_vld;
reg[6-1:0]        dout;

reg[3-1:0]        state_c;
reg[3-1:0]        state_n;

//第一段，状态跳转
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        state_c <= S0;
    end
    else begin
        state_c <= state_n;
    end
end

//第二段，组合逻辑，罗列出状态转移条件
always @(*)begin
    case(state_c)
        S0:begin
            if(S02S1_start)begin
                state_n = S1;
            end
            else if(S02S2_start)begin
                state_n = S2;
            end
            else begin
                state_n = state_c;
            end
        end
        
        S1:begin
            if(S12S2_start)begin
                state_n = S2;
            end
            else if(S12S3_start)begin
                state_n = S3;
            end
            else if(S12S0_start)begin
                state_n = S0;
            end
            else begin
                state_n = state_c;
            end
        end
        
        S2:begin
            if(S22S3_start)begin
                state_n = S3;
            end
            else if(S22S4_start)begin
                state_n = S4;
            end
            else if(S22S0_start)begin
                state_n = S0;
            end
            else begin
                state_n = state_c;
            end
        end
        
        S3:begin
            if(S32S4_start)begin
                state_n = S4;
            end
            else if(S32S0_start)begin
                state_n = S0;
            end
            else begin
                state_n = state_c;
            end
        end
        
        S4:begin
            if(S42S0_start)begin
                state_n = S0;
            end
            else begin
                state_n = state_c;
            end
        end
        
        default:begin
            state_n = S0;
        end
    endcase
end

//第三段，设计条件
assign S02S1_start = state_c == S0 && din_vld && din == 0;
assign S02S2_start = state_c == S0 && din_vld && din == 1;

assign S12S2_start = state_c == S1 && din_vld && din == 0;
assign S12S3_start = state_c == S1 && din_vld && din == 1;
assign S12S0_start = state_c == S1 && din_vld && din == 2;

assign S22S3_start = state_c == S2 && din_vld && din == 0;
assign S22S4_start = state_c == S2 && din_vld && din == 1;
assign S22S0_start = state_c == S2 && din_vld && din == 2;

assign S32S4_start = state_c == S3 && din_vld && din == 0;
assign S32S0_start = state_c == S3 && din_vld && (din == 1 || din == 2);

assign S42S0_start = state_c == S4 && din_vld && (din == 0 || din == 1 || din == 2);


assign vld0 = state_c == S0 && din_vld && din == 2;
assign vld1 = state_c == S1 && din_vld && din == 2;
assign vld2 = state_c == S2 && din_vld && din == 2;
assign vld3 = state_c == S3 && din_vld && (din == 1 || din == 2); 
assign vld4 = state_c == S4 && din_vld && (din == 0  || din == 1 || din == 2); 

//第四段，设计输出
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        dout_vld <= 0;
    end
    else if(vld0 || vld1 || vld2 || vld3 || vld4)begin
        dout_vld <= 1;
    end
    else begin
        dout_vld <= 0;
    end
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        dout <= 0;
    end
    else if(vld1  || (state_c == S4 && din_vld && din == 1))begin //这里所有判断跳进不能加上 && dout_vld ，dout 和 dout_vld 是在同一拍上有效
        dout <= 5;
    end
    else if(vld2)begin
        dout <= 10;
    end
    else if(state_c == S3 && din_vld && din == 2)begin
        dout <= 15;
    end
    else if(state_c == S4 && din_vld && din == 2)begin
        dout <= 20;
    end
    else begin
        dout <= 0;
    end
end

endmodule

测试代码：

module state_sim;

reg         clk;
reg         rst_n;
reg         din_vld;
reg[2-1:0]     din;

wire        dout_vld;
wire[6-1:0] dout;

parameter    CLK_CYCLE = 10;

initial begin
        clk = 0;
        forever begin
            #(CLK_CYCLE/2);
            clk = ~clk;
        end
end

initial begin
        rst_n = 0;
        #1;
        #(CLK_CYCLE*5);
        rst_n = 1;
end

initial begin
        #1;
        din_vld = 0;
        #(CLK_CYCLE*5);
        repeat(100)begin
            din_vld = 0;
            #(CLK_CYCLE*3);
            din_vld = 1;
            #(CLK_CYCLE);
            
            din_vld = 0;
            #(CLK_CYCLE*3);
        end            
end

initial begin
        #1;
        din = 0;
        #(CLK_CYCLE*5);
        repeat(100)begin
            #(CLK_CYCLE*3);
            din = $urandom_range(0,2);
            #(CLK_CYCLE);
            
            din = 0;
            #(CLK_CYCLE*3);
        end
end

state_test u1_inist(
                    .clk(clk),
                    .rst_n(rst_n),
                    .din_vld(din_vld),
                    .din(din),
                    .dout_vld(dout_vld),
                    .dout(dout)
                );

endmodule

仿真波形：

 

 

quartus 状态图：

 

转移条件