状态机-阶段1 练习2

题目：

 

 状态机图：

 

 

代码：

  1 //检测序列1101
  2 module state_test(
  3                     clk,
  4                     rst_n,
  5                     din,
  6                     dout
  7 );
  8 
  9 parameter    S0 = 3'b000;
 10 parameter    S1 = 3'b001;
 11 parameter    S2 = 3'b010;
 12 parameter    S3 = 3'b100;
 13 
 14 input         clk        ;
 15 input         rst_n    ;
 16 input         din        ;
 17 output        dout    ;
 18     
 19 reg            dout    ;
 20 reg [3-1:0]    state_c    ;
 21 reg [3-1:0]    state_n    ;
 22 
 23 
 24 wire         S02S1_start;
 25 wire         S12S2_start;
 26 wire         S12S0_start;
 27 wire         S22S3_start;
 28 wire         S32S0_start;
 29 
 30 //第一段，状态跳转
 31 always @(posedge clk or negedge rst_n)begin
 32     if(!rst_n)begin
 33         state_c <= S0;
 34     end
 35     else begin
 36         state_c <= state_n;
 37     end
 38 end
 39 
 40 //第二段：组合逻辑always模块，描述状态转移条件判断
 41 always @(*)begin
 42     case(state_c)
 43         S0:begin
 44             if(S02S1_start)begin
 45                 state_n = S1;
 46             end
 47             else begin
 48                 state_n = state_c;
 49             end
 50         end
 51         
 52         S1:begin
 53             if(S12S2_start)begin
 54                 state_n = S2;
 55             end
 56             else if(S12S0_start)begin
 57                 state_n = S0;
 58             end
 59             else begin
 60                 state_n = state_c;
 61             end
 62         end
 63         
 64         S2:begin
 65             if(S22S3_start)begin
 66                 state_n = S3;
 67             end
 68             else begin
 69                 state_n = state_c;
 70             end
 71         end
 72         
 73         S3:begin
 74             if(S32S0_start)begin
 75                 state_n = S0;
 76             end
 77             else begin
 78                 state_n = state_c;
 79             end
 80         end
 81         
 82         default:begin
 83             state_n = S0;
 84         end
 85     endcase
 86 end
 87 
 88 //第三段：设计转移条件
 89 assign S02S1_start = state_c == S0 && din == 1;
 90 assign S12S2_start = state_c == S1 && din == 1;
 91 assign S12S0_start = state_c == S1 && din == 0;
 92 assign S22S3_start = state_c == S2 && din == 0;
 93 assign S32S0_start = state_c == S3 && (din == 1 || din == 0);
 94 
 95 //第四段，设计输出
 96 always @(posedge clk or negedge rst_n)begin
 97     if(!rst_n)begin
 98         dout <= 0; 
 99     end
100     else if(state_c == S3 && din == 1)begin //S32S0_start && din == 1
101         dout <= 1;
102     end
103     else begin
104         dout <= 0;
105     end
106 end
107 
108 endmodule

 

测试代码：

 1 module state_sim;
 2 
 3 reg     clk;
 4 reg     rst_n;
 5 reg     din;
 6 
 7 wire     dout;
 8 
 9 parameter    CLK_CYCLE = 10;
10 
11 initial begin
12         clk = 0;
13         forever begin
14             #(CLK_CYCLE/2);
15             clk = ~clk;
16         end
17 end
18 
19 initial begin
20         rst_n = 0;
21         #1;
22         #(CLK_CYCLE*5);
23         rst_n = 1;
24 end
25 
26 initial begin
27         #1;
28         din = 0;
29         #(CLK_CYCLE*10);
30         din = 1;
31         #(CLK_CYCLE);
32         
33         din = 0;
34         #(CLK_CYCLE);
35         
36         din = 0;
37         #(CLK_CYCLE);
38         
39         din = 1;
40         #(CLK_CYCLE);
41         
42         din = 0;
43         #(CLK_CYCLE);
44         
45         din = 0;
46         #(CLK_CYCLE);
47         
48         din = 1;
49         #(CLK_CYCLE);
50         
51         repeat(100)begin
52             din = $urandom_range(0,1);
53             #(CLK_CYCLE);
54         end
55 end
56 
57 state_test u1_inist(
58                     .clk(clk),
59                     .rst_n(rst_n),
60                     .din(din),
61                     .dout(dout)
62                 );
63 
64 endmodule

仿真波形：

 

 Quartus 软件自动生成的状态图：

 

条件转移：

 

posted @ 2022-03-24 09:45  MyBooks  阅读(67)  评论(0)    收藏  举报