HDLBits Dff8ar

原始题目:

Create 8 D flip-flops with active high asynchronous reset. All DFFs should be triggered by the positive edge of clk.

Module Declaration

module top_module (
   input clk,
   input areset,   // active high asynchronous reset
   input [7:0] d,
   output [7:0] q
);

Hint

The only difference in code between synchronous and asynchronous reset flip-flops is in the sensitivity list.

题目要求创建一个异步清零端的D触发器,这并不难,但是一个细节可能会导致编译错误。一个常见的错误代码如下:

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);

    always @(posedge clk or posedge areset) begin
        if (~areset) q <= d;
        else q <= 8'b0;
    end
endmodule

提交后出现下面的报错,这个报错显得毫无道理,毕竟语法上没有啥问题。

cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct File: ...

我在Stackoverflow上找到了一个挺有说服力的解释如下:

This is more likely an issue with your synthesizer then your simulator. The likely problem is that the first code does not match any of it's templates for a synchronous flip-flop with asynchronous reset.
The common coding practice is to assign your reset logic before any other logic. This coding practice has been around for decades. I assume the rational behind this particular coding practice stems from:

  • Reset logic is critical from many designs; especially as designs get larger and more complex. It is put at the top for it importance and the fact that it usually fewer lines of code then the synchronous logic.
  • Early synthesizers were very limited and could only synthesize specific code structures.
  • The coding style has become a precedence. No one is going to change it unless you can convince and prove something else is superior or has specific advantages.

In your case, your synthesizer is doing a lint check and has determined your code is not following the conventional coding practices. The creator of your synthesizer has decided to only support the common coding structure and there is little incentive to change.
FYI: you should be assigning synchronous logic with non-blocking assignments (<=). Blocking assignments (=) should be used for combinatonal logic. If you do not follow proper coding practices you increase the risk of introducing race-conditions, RTL vs gate mismatch, and other bugs.

看起来和FPGA本身的设计有关?我们需要遵循传统。

下面是可以提交通过的代码:

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);

    always @(posedge clk or posedge areset) begin
        if (areset) q <= 8'b0;
        else q <= d;
    end
endmodule

by SDUST weilinfox

posted @ 2021-04-26 18:11  八衛門狸  阅读(80)  评论(0编辑  收藏  举报