FPGA开发（1） 

 1 `timescale 1 ns / 1 ns
 2 module system_ctrl
 3 (
 4     //globol clock
 5     input                clk,
 6     input                rst_n,
 7 
 8     //synced signal
 9     output                 clk_ref,    //clock output    
10     output                 sys_rst_n    //system reset
11 );
12 
13 //----------------------------------------------
14 //rst_n sync, only controlled by the main clk
15 reg     rst_nr1, rst_nr2;
16 always @(posedge clk)
17 begin
18     if(!rst_n)
19         begin
20         rst_nr1 <= 1'b0;
21         rst_nr2 <= 1'b0;
22         end
23     else
24         begin
25         rst_nr1 <= 1'b1;
26         rst_nr2 <= rst_nr1;
27         end
28 end
29 
30 
31 //----------------------------------
32 //component instantiation for system_delay
33 wire    delay_done;    //system init delay has done
34 system_init_delay
35 #(
36     .SYS_DELAY_TOP    (24'd2500000)
37 //    .SYS_DELAY_TOP    (24'd256)    //Just for test
38 )
39 u_system_init_delay
40 (
41     //global clock
42     .clk        (clk),
43     .rst_n        (1'b1),            //It don't depend on rst_n when power up
44     //system interface
45     .delay_done    (delay_done)
46 );
47 
48 assign    clk_ref = clk;
49 assign    sys_rst_n = rst_nr2 & delay_done;    //active High
50 
51 endmodule

 

posted @ 2016-03-03 14:42  LOOP$  阅读(205)  评论(0)    收藏  举报