摘要： Note it is not supported in verilog http://en.wikipedia.org/wiki/SystemVerilogThe preprocessor has improved `define macro-substitution capabilities, specifically substitution within literal-strings (""), as well as concatenation of multiple macro-tokens into a single word.link fromhttps:// 阅读全文

摘要： matlab commanddiary 阅读全文

摘要： error information Illegal index into array of interfacesthe reasonlink http://forums.accellera.org/topic/677-ies-102-using-config-db-to-set-array-of-interfaces/https://forum.verificationacademy.com/forum/verification-methodology-discussion-forum/uvm-forum/24462-setting-array-interfaces-uvm-config-da 阅读全文

摘要： grep -nR ' ' ./* 阅读全文

摘要： Illegal assignment to type String from class mtiUvm.uvm_pkg::uvm_analysis_port #it is really trival ap = new(.name("****"), .parent(this)); 阅读全文

摘要： Clocking block output is not legal in this # or another expression.modport / clocking block the direction is wrong for monitor 阅读全文

摘要： The qverilog command compiles (vlog), optimizes (vopt), and simulates (vsim) Verilog andSystemVerilog designs in a single step. It combines the compile, elaborate, and simulate phasestogether, as some users may be accustomed to doing with NC-Sim. This command is providedto ease these users’ transiti 阅读全文

摘要： the simple reason is the uvm_macros.svh not included in the top fileand note: there is no need to add +incdir+ to look for the svhbecause the questa will automatically fix the path when import uvm_pkg ** Error: Environment.sv(16): (qverilog-2163) Macro `uvm_component_utils is undefined.** Error: Env 阅读全文

摘要： vbird reading 阅读全文

摘要： verdiunkown host(snpslmd) Vendor daemon can't talk to lmgrd (Cannot connect to license server system./etc/hosts中的的hostname必须和hostname命令输出结果一致。FLEXlm error: -15,570. System Error: 111 "Connection refused"lmgrd -c xxx.lic 阅读全文