Testbench编写指南（2）文件的读写操作

 

Testbench编写指南（2）文件的读写操作

 

https://blog.csdn.net/FPGADesigner/article/details/80470972

 

`timescale 1 ns/1 ns

module tb_rtv();


parameter  CLK_PERIOD = 20;
parameter    RST_TIME = 3 ;

reg        clk;
reg rst_n;

reg  [15:0] D;//ltc2250采样数据
reg  [0:0] en;//from ltc2250 
reg  [1:0] state;//采样率选择，0-25MHz，1-50MHz，2-100MHz
reg  [31:0] BLT1;//在这段时间内，视为非有效波形，单位是时间，根据不同厚度调整这个时间大小
reg  [31:0] BLT2;
reg  [31:0] BLT3;
reg  [31:0] BLT4;
reg  [31:0] BLT5;
reg  [31:0] BLT6;
reg  [31:0] BLT7;

reg  [15:0] othreshold ;//外壁返回阈值，是一个固定值，只有正的
reg  [15:0] ithreshold1;
reg  [15:0] ithreshold2;
reg  [15:0] ithreshold3;
reg  [15:0] ithreshold4;
reg  [15:0] ithreshold5;
reg  [15:0] ithreshold6;
reg  [15:0] ithreshold7;

wire   [7:0] high_r;
wire   [31:0] outer;
wire   [31:0] inner1;
wire   [31:0] inner2;
wire   [31:0] inner3;
wire   [31:0] inner4;
wire   [31:0] inner5;
wire   [31:0] inner6;
wire   [31:0] inner7;

reg   [2:0]  layers;

wire   [15:0] amp;//增益


    initial begin
        clk = 0;
        forever
        #(CLK_PERIOD/2)
        clk=~clk;
    end





initial begin
rst_n =0;
en    ='d1    ;
state ='d1    ;
BLT1  ='d100  ;
BLT2  ='d50  ;
BLT3  ='d50  ;
BLT4  ='d50  ;
BLT5  ='d50  ;
BLT6  ='d50  ;
BLT7  ='d50  ;

othreshold  ='d65336 ;
ithreshold1 ='d150 ;
ithreshold2 ='d100 ;
ithreshold3 ='d100 ;
ithreshold4 ='d100 ;
ithreshold5 ='d100 ;
ithreshold6 ='d100 ;
ithreshold7 ='d100 ;

layers      ='d1   ;

#500;
rst_n=1;
#80962;
en='d0 ;

 repeat(10)begin
 #1000
 en    ='d1    ;
 #80962;
    en='d0 ;
 end 

end 




// parameter DATA_NUM=1024;
// integer i;   //数组坐标
// reg [15:0] stimulus[1:DATA_NUM];  //数组形式存储读出的数据
// initial 
// begin
    // $readmemb("D:/usms/Questa_sim/top1/Data.txt", stimulus);  //将txt文件中的数据存储在数组中
    // i = 0;
    // repeat(DATA_NUM) begin   //重复读取数组中的数据
        // i = i + 1;
        // D = stimulus[i]; 
        // #CLK_PERIOD;         //每个时钟读取一次
    // end
// end           

parameter M=16;
parameter N=4096;
reg    [M-1:0]    mem_normal    [N:1];
reg    [M-1:0]    mem    [N:1];

initial
begin
    $readmemb("D:/usms/Questa_sim/top1/DATA2.txt", mem_normal);
    // $readmemb("D:/usms/Questa_sim/top1/DATA.txt", mem); 
end
reg    [M-1:0]    data_in;
integer index = 1;

initial
begin
    
    forever
    begin
        #CLK_PERIOD; 
        data_in = mem_normal[index];
        index = (index >= N) ? 1 : index + 1;
    end    
    
    // #1000    

// repeat(10)
    // begin
        ////@(posegde clk);
        // #CLK_PERIOD; 
        // data_in = mem[index];
        // index = (index >= N) ? 1 : index + 1;
    // end
end





wire [11:0] outer_new;
rtv rtv_uut(
    . clk         (clk         ),
    .rst_n(rst_n),
    . D           (data_in           ),
    . en          (en          ),
    . state       (state       ),
    . BLT1        (BLT1        ),
    . BLT2        (BLT2        ),
    . BLT3        (BLT3        ),
    . BLT4        (BLT4        ),
    . BLT5        (BLT5        ),
    . BLT6        (BLT6        ),
    . BLT7        (BLT7        ),

    . othreshold  (othreshold  ),
    . ithreshold1 (ithreshold1 ),
    . ithreshold2 (ithreshold2 ),
    . ithreshold3 (ithreshold3 ),
    . ithreshold4 (ithreshold4 ),
    . ithreshold5 (ithreshold5 ),
    . ithreshold6 (ithreshold6 ),
    . ithreshold7 (ithreshold7 ),
        
    . high_r      (high_r      ),
    . outer       (outer       ),
    . outer_new   (outer_new   ),
    . inner1      (inner1      ),
    . inner2      (inner2      ),
    . inner3      (inner3      ),
    . inner4      (inner4      ),
    . inner5      (inner5      ),
    . inner6      (inner6      ),
    . inner7      (inner7      ),
    . layers      (layers      ),
    . amp         (amp         )
);

    endmodule