Xilinx的高质量时钟输出ODDR原语【随路时钟】【全局时钟网络】【ZC706输出时钟】【ZYNQ】

 

Xilinx的高质量时钟输出ODDR原语【随路时钟】【全局时钟网络】【ZC706输出时钟】【ZYNQ】

wire user_clk;
IBUFDS IBUFDS_inst_user_clk(
    .O(user_clk), // Buffer output
    .I(USRCLK_P_I), // Diff_p buffer input
    .IB(USRCLK_N_I) // Diff_n buffer input
);   
 
wire user_clk_bufg;
BUFG BUFG_inst_user_clk (
      .O(user_clk_bufg), // 1-bit output: Clock output
      .I(user_clk)
);
 
wire user_clk_bufg_oddr;
ODDR #(
      .DDR_CLK_EDGE("OPPOSITE_EDGE"), //"OPPOSITE_EDGE" or "SAME_EDGE"
      .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
      .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
 ) ODDR_out_clock_inst_user_clock (
     .Q(user_clk_bufg_oddr),   // 1-bit DDR output
     .C(user_clk_bufg),   // 1-bit clock input
     .CE(1'b1), // 1-bit clock enable input
     .D1(1'b1), // 1-bit data input (positive edge)
     .D2(1'b0), // 1-bit data input (negative edge)
     .R(),   // 1-bit reset
     .S()    // 1-bit set
);
   
 OBUFDS OBUFDS_inst_user_clock (
    .O (USER_SMA_CLOCK_P_O
    .OB(USER_SMA_CLOCK_N_O),     // Diff_n output
    .I (user_clk_bufg_oddr)      // Buffer input
 )

 

https://blog.csdn.net/qq_41305217/article/details/136512443