SystemVerilog -- 11.4 SystemVerilog Assertions with time delay

SystemVerilog Assertions with time delay

到目前为止，在之前的文章中，在每个时钟边沿检查了简单的布尔表达式。但是顺序检查需要几个时钟周期才能完成，并且时间延迟由符号指定。##

## Operator

如果a在任何给定时钟周期内不为高电平，则序列在同一周期内启动和失败。但是，如果a在任何时钟上为高电平，则assertion将开始并在2个时钟后，b为高电平时成功。如果b在2个时钟后为低电平，则失败。

module tb;
  bit a, b;
  bit clk;

  // This is a sequence that says 'b' should be high 2 clocks after 
  // 'a' is found high. The sequence is checked on every positive
  // edge of the clock which ultimately ends up having multiple 
  // assertions running in parallel since they all span for more 
  // than a single clock sycle.
  sequence s_ab;
    @(posedge clk) a ##2 b;
  endsequence

  // Print a display statement if the assertion passed
  assert property(s_ab)
    $display ("[%0d] Assertion passed !", $time);
  
  always #10 clk = ~clk;

  initial begin
    for (int i = 0; i < 10; i++) begin
      @(poseedge clk);
      a <= $random;
      b <= $random;
      $display ("[%0t] a=%b b=%b", $time, a, b);
    end
  end
  #20 $finish;
endmodule

Time(ns)	a	b	Sequence Start	Result
10	0		No	FAIL (Start@10, Fail@10)
30	0	0->1	No	FAIL (Start@30, Fail@30)
50	1		Yes
70	1		Yes
90	1		Yes	FAIL (Start@50, Fail@90)
110	1		Yes	PASS (Start@70, Fail@110)
130	0		No	PASS (Start@90, Fail@130)
150	1	1->0	Yes	PASS (Start@110, Fail@150)
170	1	0->1	Yes
190	1		Yes	FAIL (Start@150, Fail@190)

模拟日志

Compiler version P-2019.06-1; Runtime version P-2019.06-1; Dec 11 15:26 2019
[10]  a=0
"testbench.sv", 12: tb.unnamed$$_0: started at 10ns failed at 10ns
  Offending '$rose(a)'
[30]  a=1
[50]  a=1
[70]  a=1
[90]  a=1
[110] a=1
[130] a=1
[150] a=0
"testbench.sv", 12: tb.unnamed$$_0: started at 150ns failed at 150ns
  Offending '$rose(a)'
[170] a=1
[190] a=1
$finish called from file "testbench.sv", line 27.
$finish at simulation time        210