随笔分类 -  VHDL Coding Style

摘要：FPGA: Duplicated to reduce fanout and improve timingsexample:signal address_0 : std_logic_vector(11 downto 0);signal address_1 : std_logic_vector(11 downto 0);attribute equivalent_register_removal : string;attribute equivalent_register_removal of address_0: signal is "NO";attribute equival 阅读全文

摘要：How do I keep Xilinx XST from merging nets from my design?I'm asking and answering this question so that I can find it again in the future...How do I keep XST from merging two logically equivalent nets into one (which normally is a good idea to save resources, but may not be a good idea from a t 阅读全文

摘要：Record type的定义类似于C/C++中的结构的定义,tpye中可以包含其它已经定义的type.在此贴出一个package文件,library IEEE;use IEEE.STD_LOGIC_1164.all;package chan_pkg isconstant c_WORDS : integer := 2;constant c_32BITS_DATA : std_logic_vector := "01";constant c_64BITS_DATA : std_logic_vector := "11";type X_chan_t is reco 阅读全文

摘要：attribute keep of error_channelb: signal is "true";用法就是 keep a signal after mapping; 如果要用chipscope和在ucf文件中直接使用信号名的,可用keep这保持,这样可方便我们添加观察信号和添加约束.Often you want to assign a constraint to a particular signal in your design, or you want be able to find a particular signal in Chipscope inserter 阅读全文