随笔分类 -  fpga

摘要：一、Creat a new project，generate a new DDR3 IP，Close Project.二、打开工程文件下的 X_example_design-->simulation-->generate_sim_example_design.qpf,运行TCL脚步文件里的verilog文件三、Open modelsim,change direaction to 工程文件下的X_example_design-->simulation-->verilog-->mentor四、do run.do 阅读全文

摘要：又见SYSID问题，弄了两天都没解决，今天参照例程改了device and pin里的设置，解决问题了。顺便把数码管、led无缘无故亮的问题也解决了。DEVICE:PACKAGE:FBGAPIN COUNT:780SPEED GRADE:ANYDUAL-PURPOSE pins：DCLK:USE AS PROGRAMMING PINDATA[0]:as input tri_stateddata[1]/asd0:同上data[7..2]:use as regular i/oflash-nce/ncso:as input tri_statedother active parallet pins:. 阅读全文