摘要：Every cell has multipletiming arcs. For example, a combinational logic cell, such as and, or, nand, nor, adder cell, has timing arcs from each input to each output of the cell. Sequential cells such as flip-flops have timing arcs from the clock to the outputs and timing constraints for the data pins 阅读全文

摘要：静态时序分析（Static Timing Analysis---STA)的前提是同步逻辑设计：通过路径计算延迟的总和，并比较相对于预定义时钟的延迟. 一 基础知识 1 同步逻辑延时模型 如上图所示，T = tCO+tDELAY+tSU。时钟周期大于T，触发器正常工作；时钟周期小于T，不满足建立时间，触发器可能经历亚稳态。即最高时钟频率f = 1/T。 若考虑到时钟偏斜skew,则如下图... 阅读全文