摘要:
Verilog 常见错误汇总 1.Found clock-sensitive change during active clock edge at time <time> on register "<name>" 原因:vector source file中时钟敏感信号(如:数据,允许端,清零,同步 阅读全文
摘要:
/usr/include/asm/errno.h#define EPERM 1 /* Operation not permitted */操作不允许#define ENOENT 2 /* No such file or directory */文件/路径不存在#define ESRCH 3 /* N 阅读全文