Synplify SCOPE 属性1

 

Attribute/Directive	Description
black_box_pad_pin Directive	Specifies that a pin on a black box is an I/O pad. It is applied to a component, architecture, or module, with a value that specifies the set of pins on the module or entity.
black_box_tri_pins Directive	Specifies that a pin on a black box is a tristate pin. It is applied to a component, architecture, or module, with a value that specifies the set of pins on the module or entity.
full_case Directive 表明 case 语句已经覆盖所有情况	Specifies that a Verilog case statement has covered all possible cases.
loop_limit Directive (Verilog)	Specifies a loop iteration limit for for loops.
parallel_case Directive 要求综合case语句的时候产生并行MUX结构而不是优先级编码结构	Specifies a parallel multiplexed structure in a Verilog case statement, rather than a priority-encoded structure.
syn_allowed_resources Attribute	Specifies allowed resources for compile points (applies to all Virtex, and Spartan-II, Spartan-IIE, Spartan-IIE Automotive, Spartan-3, Spartan-3 Automotive, and Spartan-3E technologies). The value assigned to a given compile point includes the resources used by its children (at all levels). Compile points are not supported in the Synplify tool.
syn_allow_retiming Attribute	Specifies whether registers can be moved during retiming (applies to all Virtex technologies and the Spartan-II, Spartan-IIE, Spartan-IIE Automotive, Spartan-3, Spartan-3 Automotive, and Spartan-3E technologies). The Synplify software does not support retiming.
syn_black_box Directive	Defines a black box for synthesis.
syn_clean_reset Attribute	Changes asynchronous reset registers, which cannot go into DSP48 blocks, into synchronous reset logic. Xilinx Virtex-4 and Virtex-5 only.
syn_diff_io Attribute	Controls the inference of I/O buffers.
syn_direct_enable Attribute/Directive	Identifies which signal to use as the enable input to an enable flip-flop when multiple candidates are possible.
syn_dspstyle Attribute	In Virtex-4 and Virtex-5 designs, determines if an operator, register, or module/architecture is placed in the DSP48 component.
syn_edif_bit_format Attribute	Controls the character formatting and style of bus signal names, port names, and vector ranges in the EDIF output file.
syn_edif_scalar_format Attribute	Controls the character formatting of scalar signal and port names in the EDIF output file.
syn_encoding Attribute	Specifies the encoding style for state machines.
syn_enum_encoding Directive	Specifies the encoding style for enumerated types (VHDL only).
syn_forward_io_constraints Attribute	Enables forward annotation of I/O constraints to Xilinx place-and-route tools.
syn_global_buffers Attribute	Sets the number of global buffers to use in a design.
syn_hier Attribute	Controls the handling of hierarchy boundaries of a module or component during optimization and mapping.
syn_insert_buffer Attribute	Inserts a clock buffer according to the specified value.
syn_isclock Directive	Specifies that a black-box input port is a clock, even if the name does not indicate it is one.
syn_keep Directive	Prevents the internal signal from being removed during synthesis and optimization.
syn_loc Attribute	Specifies pin locations for I/O pins and cores, and forward-annotates this information to the place-and-route tool.
syn_maxfan Attribute	Overrides the default fanout guide for an individual input port, net, or register output.
syn_multstyle Attribute	Determines implementation style for multipliers in Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5, and Spartan-3 designs.
syn_netlist_hierarchy Attribute	Determines if the EDIF output netlist is flat or hierarchical.
syn_noarrayports Attribute	Prevents the ports in the EDIF output netlist from being grouped into arrays, and leaves them as individual signals.
syn_noclockbuf Attribute	Controls the automatic insertion of global clock buffers.
syn_noprune Directive	Controls the automatic removal of instances that have outputs that are not driven.
syn_pad_type Attribute	Specifies an I/O buffer standard. (Spartan-3/3E, Virtex-II, Virtex-II Pro, Virtex-4, and Virtex-5)
syn_pipeline Attribute	Specifies that registers be moved into ROMs or multipliers to improve frequency. This attribute applies to all XC4000 and Virtex technologies and to the Spartan-II, Spartan-IIE, Spartan-IIE Automotive, Spartan-3, Spartan-3 Automotive, and Spartan-3E technologies. The Synplify software does not support pipelining.
syn_preserve Directive	Prevents sequential optimizations across a flip-flop boundary during optimization, and preserves the signal.
syn_probe Attribute	Adds probe points for testing and debugging. The Synplify software does not support probe point insertion.
syn_ramstyle Attribute	Determines the way in which RAMs are implemented.
syn_reference_clock Attribute	Specifies a clock frequency other than that implied by the signal on the clock pin of the register.
syn_replicate Attribute	Disables replication.
syn_romstyle Attribute (Xilinx)	Determines how ROM architectures are implemented.
syn_sharing Directive	Specifies resource sharing of operators.
syn_srlstyle Attribute	Determines how to implement the sequential shift (seqShift) components. This attribute applies to Virtex technologies.
syn_state_machine Directive	Determines if the FSM Compiler extracts a structure as a state machine.
syn_tco<n> Directive	Defines timing clock to output delay through the black box. The n indicates a value between 1 and 10.
syn_tpd<n> Directive	Specifies timing propagation for combinational delay through the black box. The n indicates a value between 1 and 10.
syn_tristate Directive	Specifies that a black-box pin is a tristate pin.
syn_tristatetomux Attribute	Converts tristate drivers that drive nets below a certain limit to multiplexers. This only applies to the XC4000 and Virtex technologies.
syn_tsu<n> Directive	Specifies the timing setup delay for input pins, relative to the clock. The n indicates a value between 1 and 10.
syn_useenables Attribute	Prevents generation of registers with clock enable pins.
syn_useioff Attribute (Xilinx) 将寄存器插入到 I/O 以缩短信号经过 I/O block 的延时	Packs flip-flops in the I/Os to improve input/output path timing.
translate_off/translate_on Directive	Specifies sections of code to exclude from synthesis, such as simulation-specific code.
xc_alias Attribute	Changes the cell name in XNF for all technologies except Virtex.
xc_area_group Attribute	Assigns a compile point to a Xilinx area group (applies to all Virtex technologies and the Spartan-II, Spartan-IIE, Spartan-IIE Automotive, Spartan-3, Spartan-3 Automotive, and Spartan-3E technologies). The Synplify software does not support compile points.
xc_clockbuftype Attribute	Specifies that a clock port use the Clock Delay Locked Loop primitive, CLKDLL, in Virtex designs.
xc_fast Attribute 提高输出驱动，加速输出信号的0/1电平转换	Speeds up the transition time of the output driver. The Synplify Premier software does not support this attribute.
xc_fast_auto Attribute	Controls the instantiation of fast output buffers in Virtex designs.
xc_global_buffers Attribute	Controls the number of global buffers to use in a design.
xc_isgsr Directive	Specifies that a black-box port is connected to an internal STARTUP block, and prevents the synthesis tool from inferring a STARTUP block. This attribute applies to the XC4000 technologies. The Synplify Premier software does not support this attribute.
xc_loc Attribute	Specifies the placement of ports and design units.
xc_map Attribute	Specifies the LUT primitive in all Virtex and the Spartan-II, Spartan-IIE, Spartan-IIE Automotive, Spartan-3, Spartan-3 Automotive, and Spartan-3E designs. In Synplify and Synplify Pro, it also specifies the Xilinx fmap or hmap primitive in XC4000 designs.
xc_modular_region Attribute	Specifies the physical location of a modular region for a modular flow design (applies to all Virtex technologies and the Spartan-II, Spartan-IIE, Spartan-IIE Automotive, Spartan-3, Spartan-3 Automotive, and Spartan-3E technologies). This attribute is used to synthesize individual modules in the modular design flow. The Synplify software does not support modular design.
xc_nodelay Attribute	Controls the Xilinx insertion of input delay for flip-flops and latches. The Synplify Premier software does not support this attribute.
xc_padtype Attribute	Specifies an I/O buffer standard in Virtex designs.
xc_pullup/xc_pulldown Attribute 指定上拉或下拉端口	Specifies that a port is a pullup or pull-down port.
xc_rloc Attribute	Specifies the relative locations of all instances with the same xc_uset attribute value. This attribute applies to Xilinx technologies with the exception of CPLD.
xc_use_keep_hierarchy Attribute	Preserves the hierarchy of the marked module for diagnostics and timing simulation.
xc_slow Attribute	Specifies a slow transition time for the driver of an output port. This attribute applies to XC4000 technologies. The Synplify Premier software does not use this attribute.
xc_use_keep_hierarchy Attribute	Marks a hierarchical block or compile point as a module that can be implemented independently by the P&R tool This attribute is only available with the Synplify Pro and Synplify Premier tools.
xc_use_xmodule Attribute	Marks a hierarchical block or compile point as a module that can be implemented independently by the P&R tool This attribute is only available with the Synplify Pro and Synplify Premier tools.
xc_uset Attribute	Assigns a group name to component instances.
xc_use_timespec_for_io Attribute	Uses the TIMESPEC command to write out I/O constraints. The Synplify software does not use this attribute.