verilog （02/13/2014）
摘要：
Corrections:1. Besides inputs, combinational outputs are not synchronized by clock.Points:1. We prefer to draw state diagram as follows:Circles contain state name, something to do in the state. something to do in the circles refer to update the register variable, usually we write transition conditio 阅读全文
posted @ 2014-02-14 05:07 大米808 阅读(325) 评论(0) 推荐(0)
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