verilog （02/13/2014）

Corrections:

1. Besides inputs, combinational outputs are not synchronized by clock.

Points:

1. We prefer to draw state diagram as follows:

• Circles contain state name, something to do in the state. something to do in the circles refer to update the register variable, usually we write transition condition
• transition arrows contain inputs, outputs.

2. We prefer to write verilog codes which is based on SM like this:

• using at least two always blocks, one is SM+NSL, the other is OFL.
• OFL is written based on transition arrow

3. There are two ways to understand count variable.

• count means that already occured how many circles
• each substate has a specific count like S0₀->countS0=0