【Verilog】Gray Code Counter 格雷码计数器Zz

Gray  code counters (having one bit change per counter transition) are often used in FIFO design and digital communication.

Here I will show two styles gray code counter.

Style #1 

First style gray code counter uses a single set of flip-flops as the Gray code register with accompanying Gray-tobinary conversion, binary increment, and binary-to-Gray conversion.  

 

 

• module gray_counter(
  
•         input iclk,
  
•         input irst_n,
  
•         input ivalid,
  
•         output reg [3:0] gray);
  
• 
  
• wire [3:0] bin_counter;
  
• wire [3:0] gray_counter;
  
•  
  
• reg  [3:0] G2B_counter;
  
• 
  
• // convert gray to  bin;
  
• always@(ocounter)
  
• begin
  
•     G2B_counter[3] = gray[3];
  
•     G2B_counter[2] = gray[2] ^ G2B_counter[3];
  
•     G2B_counter[1] = gray[1] ^ G2B_counter[2];
  
•     G2B_counter[0] = gray[0] ^ G2B_counter[1];
  
• end
  
• 
  
• //binary counter increased by one
  
• assign bin_counter = bin_counter +ivalid;
  
• 
  
• //convert bin to gray 
  
• assign gray_counter = (bin_counter >>1) ^ bin_counter;
  
• 
  
• always@(posedge iclk or negedge irst_n)
  
• begin
  
•     if(!irst_n)
  
•     begin
  
•         gray <= 4'b0;
  
•     end
  
•     else
  
•     begin
  
•         gray <= gray_counter;
  
•     end
  
• end
  
• 
  
• endmodule
  
• 

 

Style #2

A second Gray code counter style, the one described below, uses two sets of registers, one a binary counter and a second to capture a binary-to-Gray converted value. The intent of this Gray code counter style #2 is to utilize the binary carry structure, simplify the Gray-to-binary conversion; reduce combinational logic, and increase the upper frequency limit of the Gray code counter.

 

 

 

 1module graycounter(
 2           input iclk,
 3           input irst_n,
 4           input ivalid,
 5           output     [ADDSIZE-1 : 0]  bin,
 6           output reg [ADDSIZE : 0]  gray);
 7
 8parameter ADDSIZE = 4;
 9
10wire[ADDSIZE : 0] binnext;
11wire[ADDSIZE : 0] graynext;
12reg[ADDSIZE : 0] bin_o;
13
14assign binnext = bin_o + ivalid;
15
16assign graynext = (binnext >>1) ^ binnext;
17
18assign bin = bin_o[ADDSIZE-1 : 0];
19
20always@(posedge iclk or negedge irst_n )
21if(!irst_n)
22    {bin_o, gray} <= 0;
23else
24    {bin_o, gray} <= {binnext, graynext};
25
26
27endmodule
28
29
30
31

 

Reference:

1.Vijay A. Nebhrajani," Asynchronous FIFO Architectures" part2 

2. Clifford E. Cummings, Sunburst Design, Inc " Simulation and Synthesis Techniques for Asynchronous
FIFO Design"