one tip for HDL coding

In previos work, when I encounter the situation counter reach full state (such as counter[3:0] reaches 4'b1111), I used to manually flip counter to zeros on next rsing clock edge . However, I have ignored the fact that counter will automatically overflow on next rising clock edge when it reaches full state.

 Codes below are part of synchronous FIFO design, I will release the rest when I finish testing.

Previous  coding style

 

• begin
  
• if(wr_addr != 4'b1111)
  
•     begin
  
•     if(rd_addr != wr_addr + 4'b0001)
  
•         ns = wcntstate;
  
•     else
  
•         ns = fullstate;
  
•     end
  
• else
  
•         begin
  
•         if(rd_addr != 4'b0000)
  
•             ns = wcntstate;
  
•         else
  
•             ns = fullstate;
  
•         end                    
  
• end 
  

 modified coding style

 

1begin
2    if(wr_addr != rd_addr + 4'b0001)
3        ns = wcntstate;
4    else
5        ns = emptystate;
6end