50mhz 时钟检测目标时钟是否为100mhz .检测正确输出标志信号，否则输出目标时钟频率

编写一个频率检测模块，输入端口：50M时钟，待检测时钟（范围1M-200M）

输入端口A：50M时钟

输入端口B：被测时钟

输入端口C：复位信号

输出端口D：频率值（单位Mhz

module time_detect(
input clk_ref_in   ,   //参考时钟50M
input clk_in      ,   //待测时钟
input rst         ,
output [15:0] number //
)；
 
//=======================================================================\
//****************************    寄存器定义      *************************
 
reg [7:0]  clk_cnt = 0;
reg      high_lev = 0;
reg      high_lev_ff1;
reg      high_lev_ff2;
reg      high_lev_ff3;
reg [15:0] clk_ref_cnt = 0;
reg [15:0] clk_ref_cnt_lat = 0;
reg [15:0] clk_F = 0
 
//============================  clk_in时钟域  ============================\
/********  clk_in：1~200M,先降频,经200倍分频后的时钟不大于1M    ************/ 
//计数器
always @ (posedge clk_in or posedge rst)
begin
 if(rst)
     clk_cnt <= 0
 else if(clk_cnt == 199)
    clk_cnt <= 0;
 else 
  clk_cnt <= clk_cnt + 1;
end
 
//分频输出
always @ (posedge clk_in or posedge rst)
begin 
 if(rst)
     high_lev <= 0;
 else if(clk_cnt == 99)
     high_lev <= 1;
 else if(clk_cnt == 199)
  high_lev <= 0;
 else;
end
 
 
//=========================   clk_ref_in参考时钟域 =========================\
/*对输入分频时钟作跨时钟域处理：大三拍*/
always @ (posedge clk_ref_in) 
begin
 high_lev_ff1 <= high_lev;
 high_lev_ff2 <= high_lev_ff1;
 high_lev_ff3 <= high_lev_ff2;
end
 
/*ref时钟域下对分频后的时钟高电平进行计数*/
always @ (posedge clk_ref_in or posedge rst)
begin
 if(rst)
         clk_ref_cnt <= 0;
 else if(high_lev_ff3)
         clk_ref_cnt <= clk_ref_cnt + 1;
 else
         clk_ref_cnt <= 0;
end
 
/*用一个锁存器clk_ref_cnt_lat锁存高电平计数最大值：即将分频时钟下降沿达到最大值*/
always @ (posedge clk_ref_in or posedge rst)
begin 
 if(rst)
      clk_ref_cnt_lat <= 0;
 else if({high_lev_ff3,high_lev_ff2} == 2'b10)
      clk_ref_cnt_lat <= clk_ref_cnt;
 else 
end
 
/*计算频率*/
always @ (posedge clk_ref_in or posedge rst)
begin
 if(rst)
       clk_F <= 0;
 else
       clk_F <= 5000/clk_ref_cnt_lat;
end  
 
assign number = clk_F;
emdmodule