1. 硬件相关 - 随笔分类(第5页) - QIYUEXIN

6.4 Data Types

摘要：Table 6-1 lists the size, representation, and range of each scalar data type for the C28x compiler. Many ofthe range values are available as standard 阅读全文

posted @ 2017-02-12 20:11 QIYUEXIN 阅读(239) 评论(0) 推荐(0)

9.3.2 The force and release procedural statements

摘要：Frm： IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language Another form of procedural continuous assignment is provided by the for 阅读全文

posted @ 2017-02-10 18:17 QIYUEXIN 阅读(336) 评论(0) 推荐(0)

3.7.4 Tri0 and tri1 nets

摘要：Frm: IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language The tri0 and tri1 nets model nets with resistive pulldown and resistive 阅读全文

posted @ 2017-02-10 12:37 QIYUEXIN 阅读(1002) 评论(0) 推荐(0)

9.3.1 The assign and deassign procedural statements

摘要：IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language The assign procedural continuous assignment statement shall override all pro 阅读全文

posted @ 2017-02-10 11:25 QIYUEXIN 阅读(353) 评论(0) 推荐(0)

10. Tasks and functions

摘要：Frm: IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language 10. Tasks and functions Tasks and functions provide the ability to exec 阅读全文

posted @ 2017-02-10 09:28 QIYUEXIN 阅读(397) 评论(0) 推荐(0)

6.1.2 The continuous assignment statement

摘要：Frm: IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language The continuous assignment statement shall place a continuous assignment 阅读全文

posted @ 2017-02-09 23:04 QIYUEXIN 阅读(525) 评论(0) 推荐(0)

Quartus II 使用 modelsim 仿真

摘要：Quartus II 使用 modelsim 仿真阅读全文

posted @ 2017-02-09 22:00 QIYUEXIN 阅读(16870) 评论(0) 推荐(1)

与DSP通信时，RD&WR信号

摘要：/////////////////////////////////////////////////////////// reg [ 1:0] rd,wr; reg [15:0] dsp_data_out; assign DSP_D = (DSP_WE && !DSP_RD) ? dsp_data_out:16'hzzzz; // Below is the communication... 阅读全文

posted @ 2017-02-09 15:46 QIYUEXIN 阅读(1145) 评论(0) 推荐(0)

4.2.1 Vector bit-select and part-select addressing

摘要：Frm:IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language Bit-selects extract a particular bit from a vector net, vector reg, inte 阅读全文

posted @ 2017-02-09 09:36 QIYUEXIN 阅读(1937) 评论(0) 推荐(0)

QIYUEXIN

随笔分类 - 1. 硬件相关