基于DE0的VGA测试

本次实验用的VGA是HPw17e电脑显示器，其分辨率为1440×900@60，系统时钟106.47MHZ

时序如下：

　　　　　　　　同步脉冲FRONT　　　　后沿SYNC　　显示脉冲ACT　　前沿BACK　　帧长TOTAL

行时序HSYNC　　　　152　　　　　　　　232　　　　　　1440　　　　80　　　　　　1904

列时序VSYNC　　　　3　　　　　　　　　　28　　　　　　900　　　　　1　　　　　　  932

Timequest约束

## Generated SDC file "vga.sdc"

## Copyright (C) 1991-2008 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions 
## and other software and tools, and its AMPP partner logic 
## functions, and any output files from any of the foregoing 
## (including device programming or simulation files), and any 
## associated documentation or information are expressly subject 
## to the terms and conditions of the Altera Program License 
## Subscription Agreement, Altera MegaCore Function License 
## Agreement, or other applicable license agreement, including, 
## without limitation, that your use is for the sole purpose of 
## programming logic devices manufactured by Altera and sold by 
## Altera or its authorized distributors.  Please refer to the 
## applicable agreement for further details.


## VENDOR  "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 8.1 Build 163 10/28/2008 SJ Full Version"

## DATE    "Tue Jan 18 15:16:36 2011"

##
## DEVICE  "EP3C16F484C6"
##


#**************************************************************
# Time Information
#**************************************************************

set_time_format -unit ns -decimal_places 3



#**************************************************************
# Create Clock
#**************************************************************

create_clock -name {clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]


#**************************************************************
# Create Generated Clock
#**************************************************************
derive_pll_clocks


#**************************************************************
# Set Clock Latency
#**************************************************************



#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty


#**************************************************************
# Set Input Delay
#**************************************************************



#**************************************************************
# Set Output Delay
#**************************************************************



#**************************************************************
# Set Clock Groups
#**************************************************************



#**************************************************************
# Set False Path
#**************************************************************



#**************************************************************
# Set Multicycle Path
#**************************************************************



#**************************************************************
# Set Maximum Delay
#**************************************************************



#**************************************************************
# Set Minimum Delay
#**************************************************************



#**************************************************************
# Set Input Transition
#**************************************************************

verilog代码文件

module vga
(
    input CLOCK_50,
    input rst_n,
    output VGA_HS,
    output VGA_VS,
    output reg [3:0] VGA_R,
    output reg [3:0] VGA_G,
    output reg [3:0] VGA_B
);
///////////////////////////////////////////////////////////////////
//===========================================================================
// PARAMETER declarations
//===========================================================================
//    Horizontal    Parameter
parameter    H_FRONT    =    152;
parameter    H_SYNC    =    232;
parameter    H_BACK    =    80;
parameter    H_ACT    =    1440;
parameter    H_VALID    =    H_FRONT+H_SYNC;
parameter    H_TOTAL    =    H_FRONT+H_SYNC+H_BACK+H_ACT;

//    Vertical Parameter
parameter    V_FRONT    =    3;
parameter    V_SYNC    =    28;
parameter    V_BACK    =    1;
parameter    V_ACT    =    900;
parameter    V_VALID    =    V_FRONT+V_SYNC;
parameter    V_TOTAL    =    V_FRONT+V_SYNC+V_BACK+V_ACT;
//===============================================================================
wire CLK_106;

PLL    PLL_inst (
    .inclk0 ( CLOCK_50 ),
    .c0 ( CLK_106 )
    );

assign clk = CLK_106;
//--------------------------------------------------
reg[10:0] x_cnt;    //行坐标
reg[10:0] y_cnt;    //列坐标

always @ (posedge clk or negedge rst_n)
    if(!rst_n) x_cnt <= 11'd0;
    else if(x_cnt == H_TOTAL-1) x_cnt <= 11'd0;
    else x_cnt <= x_cnt+1'b1;

always @ (posedge clk or negedge rst_n)
    if(!rst_n) y_cnt <= 10'd0;
    else if(y_cnt == V_TOTAL-1) y_cnt <= 10'd0;
    else if(x_cnt == H_TOTAL-1) y_cnt <= y_cnt+1'b1;

//--------------------------------------------------
wire valid;    //有效显示区标志

assign valid = (x_cnt >= H_VALID) && (x_cnt <= H_VALID+H_ACT) 
            && (y_cnt >= V_VALID) && (y_cnt <= V_VALID+V_ACT); 

wire[10:0] xpos,ypos;    //有效显示区坐标

assign xpos = x_cnt-H_VALID;
assign ypos = y_cnt-V_VALID;

//--------------------------------------------------
reg hsync_r,vsync_r;    //同步信号产生

always @ (posedge clk or negedge rst_n)
    if(!rst_n) hsync_r <= 1'b1;
   // else if(x_cnt == H_FRONT-1) hsync_r <= 1'b0;    //产生hsync信号
    //else if(x_cnt == H_FRONT+H_SYNC-1) hsync_r <= 1'b1;
    else if(x_cnt == 0) hsync_r <= 1'b0;    //产生hsync信号
    else if(x_cnt == H_FRONT-1) hsync_r <= 1'b1;
 
always @ (posedge clk or negedge rst_n)
    if(!rst_n) vsync_r <= 1'b1;
   // else if(y_cnt == V_FRONT-1) vsync_r <= 1'b0;    //产生vsync信号
    //else if(y_cnt == V_FRONT+V_SYNC-1) vsync_r <= 1'b1;
    else if(y_cnt == 0) vsync_r <= 1'b0;    //产生vsync信号
    else if(y_cnt == V_FRONT-1) vsync_r <= 1'b1;

assign VGA_HS = hsync_r;
assign VGA_VS = vsync_r;

//--------------------------------------------------
    //显示一个矩形框
wire a_dis,b_dis,c_dis,d_dis;    //矩形框显示区域定位

assign a_dis = ( (xpos>=200) && (xpos<=220) ) 
                &&    ( (ypos>=140) && (ypos<=460) );
                
assign b_dis = ( (xpos>=580) && (xpos<=600) )
                && ( (ypos>=140) && (ypos<=460) );

assign c_dis = ( (xpos>=220) && (xpos<=580) ) 
                &&    ( (ypos>140)  && (ypos<=160) );
                
assign d_dis = ( (xpos>=220) && (xpos<=580) )
                && ( (ypos>=440) && (ypos<=460) );

    //显示一个小矩形
wire e_rdy;    //矩形的显示有效矩形区域

assign e_rdy =(xpos>=385)&&(xpos<=415)&&(ypos>=285)&&(ypos<=315);


//-------------------------------------------------- 
//r,g,b控制液晶屏颜色显示，背景显示蓝色，矩形框显示红蓝色
/*
assign VGA_R = valid ?  {3'b000,e_rdy} : 4'd0;
assign VGA_G = valid ?  {3'b000,(a_dis | b_dis | c_dis | d_dis)} : 4'd0;
assign VGA_B = valid ? ~{3'b000,(a_dis | b_dis | c_dis | d_dis)} : 4'd0;  

assign VGA_R = valid ?  4'b0000 : 4'd0;
assign VGA_G = valid ?  4'b0000 : 4'd0;
assign VGA_B = valid ?  4'b1111 : 4'd0;
*/
always @ (posedge clk or negedge rst_n)
    if(!rst_n)
        {VGA_R[3:0],VGA_G[3:0],VGA_B[3:0]} <= 12'd0;
    else if(valid)
        begin
            VGA_R <= {4{e_rdy}};
            VGA_G <= {4{(a_dis | b_dis | c_dis | d_dis)}};
            VGA_B <= ~{4{(a_dis | b_dis | c_dis | d_dis)}};

        end
    else
        {VGA_R[3:0],VGA_G[3:0],VGA_B[3:0]} <= 12'd0;

endmodule