PS2解码

PS2键盘：明确接线关系，只需接4根线，VCC要+5V，刚刚又测试过，3.3V也可以用。时钟和数据线要用bidir双向口线，FPGA可以不用外接上拉电阻。另外，USB键盘也可以用，只要用一个转接头转成PS2即可。

键值查表

PS2键盘解码

其中detect.v模块

module detect
(
    input clk,
    input rst_n,
    input ps2_clk_pin_in,
    output H2L_sig
);

 reg H2L_F1,H2L_F2;

 always @ (posedge clk,negedge rst_n)
 begin
    if(!rst_n)
        begin
            H2L_F1 <= 1'b1;
            H2L_F2 <= 1'b1;
        end
        else
        begin
            H2L_F1 <= ps2_clk_pin_in;
            H2L_F2 <= H2L_F1;
        end
end 

assign H2L_sig = H2L_F2&(~H2L_F1);

endmodule 

解码模块--ps2接受模块

module decode
(
    input   clk,
    input   rst_n,
    input   H2L_Sig,
    input   data_in,
    output  [7:0] ps2_data,
    output  ps2_done_sig
);

reg [7:0] rdata;
reg [4:0] i;
reg isshift;
reg isdone;

always @ (posedge clk,negedge rst_n)
begin
    if(!rst_n)
    begin
        rdata <= 8'b0;
        i   <=5'b0;
        isdone <= 1'b0;
    end
    else
        case(i)
            5'd0:
                if(H2L_Sig)
                    i <= i+1'b1;
            5'd1,5'd2,5'd3,5'd4,5'd5,5'd6,5'd7,5'd8:
                if(H2L_Sig)
                begin
                    i <= i+1'b1;
                    rdata[i-1] <= data_in;
                end
            5'd9,5'd10:
                if(H2L_Sig)
                    i <= i +1'b1;
            5'd11:
                if(rdata==8'hF0)
                    i<=5'd12;
                else
                    i<=5'd23;
            5'd12,5'd13,5'd14,5'd15,5'd16,5'd17,5'd18,5'd19,5'd20,5'd21,5'd22:
                if(H2L_Sig)
                    i <= i+1'b1;
            5'd23:
                begin
                    i<=i+1'b1;
                    isdone <= 1'b1;
                end
            5'd24:
                begin
                    i<=5'd0;
                    isdone <= 1'b0;
                end
        endcase
end

assign ps2_data =rdata;
assign ps2_done_sig = isdone;

endmodule 

控制模块--与FIFO的接口模块

module control
(
    input clk,
    input rst_n,
    input done_sig,
    input [7:0] ps2_data,
    input full_sig,
    output write_req,
    output [7:0] fifo_write_data
);

reg [1:0] i;
reg isreq;

always @ (posedge clk,negedge rst_n)
    if(!rst_n)
    begin
        i <= 2'b0;
        isreq <= 1'b0;
    end 
    else
        case(i)
            0:
                if(done_sig && (!full_sig))
                    i <= i+1'b1;
            1:
                begin
                    isreq <= 1'b1;
                    i <= i+1'b1;
                end 
            2:
                begin
                    isreq <= 1'b0;
                    i <= 2'b0;
                end
         endcase

assign fifo_write_data =ps2_data;
assign write_req = isreq;

endmodule 

 FPGA Prototyping By Verilog Examples 中的PS2解码模块

//Listing 9.1
module ps2_rx
   (
    input wire clk, reset,
    input wire ps2d, //ps2 data
    input wire ps2c, //ps2 clk
    input wire rx_en,
    output reg rx_done_tick,
    output wire [7:0] dout
   );

   // symbolic state declaration
   localparam [1:0]
      idle = 2'b00,
      dps  = 2'b01,
      load = 2'b10;

   // signal declaration
   reg [1:0] state_reg, state_next;
   reg [7:0] filter_reg;
   wire [7:0] filter_next;
   reg f_ps2c_reg;
   wire f_ps2c_next;
   reg [3:0] n_reg, n_next;
   reg [10:0] b_reg, b_next;
   wire fall_edge;

   // body
   //=================================================
   // filter and falling-edge tick generation for ps2c
   //=================================================
   always @(posedge clk, posedge reset)
   if (reset)
      begin
         filter_reg <= 0;
         f_ps2c_reg <= 0;
      end
   else
      begin
         filter_reg <= filter_next;
         f_ps2c_reg <= f_ps2c_next;
      end

   assign filter_next = {ps2c, filter_reg[7:1]};
   assign f_ps2c_next = (filter_reg==8'b11111111) ? 1'b1 :
                        (filter_reg==8'b00000000) ? 1'b0 :
                         f_ps2c_reg;
   assign fall_edge = f_ps2c_reg & ~f_ps2c_next;

   //=================================================
   // FSMD
   //=================================================
   // FSMD state & data registers
   always @(posedge clk, posedge reset)
      if (reset)
         begin
            state_reg <= idle;
            n_reg <= 0;
            b_reg <= 0;
         end
      else
         begin
            state_reg <= state_next;
            n_reg <= n_next;
            b_reg <= b_next;
         end
   // FSMD next-state logic
   always @*
   begin
      state_next = state_reg;
      rx_done_tick = 1'b0;
      n_next = n_reg;
      b_next = b_reg;
      case (state_reg)
         idle:
            if (fall_edge & rx_en)
               begin
                  // shift in start bit
                  b_next = {ps2d, b_reg[10:1]};
                  n_next = 4'b1001;
                  state_next = dps;
               end
         dps: // 8 data + 1 parity + 1 stop
            if (fall_edge)
               begin
                  b_next = {ps2d, b_reg[10:1]};
                  if (n_reg==0)
                     state_next = load;
                  else
                     n_next = n_reg - 1;
               end
         load: // 1 extra clock to complete the last shift
            begin
               state_next = idle;
               rx_done_tick = 1'b1;
            end
      endcase
   end
   // output
   assign dout = b_reg[8:1]; // data bits

endmodule