c111
/**
* @details: This function is Uart2 Init for RS485
*/
void Uart2_Init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable UART module clock */
CLK_EnableModuleClock(UART2_MODULE);
/* Select UART module clock source and UART module clock divider */
CLK_SetModuleClock(UART2_MODULE, CLK_CLKSEL3_UART2SEL_HIRC, CLK_CLKDIV4_UART2(1));
/* Reset UART2 */
SYS_ResetModule(UART2_RST);
/* Configure UART2 and set UART2 Baudrate */
UART_Open(UART2, UART2_BAUD);
UART_SetLineConfig(UART2, 0, UART_WORD_LEN_8, UART_PARITY_NONE, UART_STOP_BIT_1);
/* Enable RDA\Time-out\LIN Interrupt */
#if UART2_IRQ
//UART_ENABLE_INT(UART2, (UART_INTEN_RDAIEN_Msk));
UART_ENABLE_INT(UART2, (UART_INTEN_TXENDIEN_Msk));
NVIC_EnableIRQ(UART2_IRQn);
NVIC_SetPriority(UART2_IRQn, 6);
#endif
/*UART2 IN PULL_UP */
GPIO_SetPullCtl(PB, 0x30, GPIO_PUSEL_PULL_UP);
/* Set multi-function pins for UART2 RXD and TXD */
SET_UART2_RXD_PB4();
SET_UART2_TXD_PB5();
/* Enable Channel_2 Channel_3 Interrupt */
/* 使能UART2接收超时中断 */
PDMA_EnableInt(PDMA0,2, PDMA_INT_TRANS_DONE);
PDMA_EnableInt(PDMA0,3, PDMA_INT_TIMEOUT);
NVIC_SetPriority(PDMA0_IRQn, 6);
NVIC_EnableIRQ(PDMA0_IRQn);
//RS485_Channel2_EN_PIN PC11=1 SEND; PC11=0 RECV;
GPIO_SetMode(PC, BIT11, GPIO_MODE_OUTPUT);
GPIO_SetSlewCtl(PC, BIT11, GPIO_SLEWCTL_FAST);
/* Lock protected registers */
SYS_LockReg();
//UART2发送完成信号量
if(UART2_Transfer_Done_BinarySemHandle ==NULL){
UART2_Transfer_Done_BinarySemHandle = xSemaphoreCreateBinary();
if(UART2_Transfer_Done_BinarySemHandle ==NULL){
RS_LOGE("UART2_Transfer_Done_BinarySemHandle xSemaphoreCreateBinary failed!");
}
}
//UART2接收完成信号量
if(UART2_Recv_Done_BinarySemHandle ==NULL){
UART2_Recv_Done_BinarySemHandle = xSemaphoreCreateBinary();
if(UART2_Recv_Done_BinarySemHandle ==NULL){
RS_LOGE("UART2_Recv_Done_BinarySemHandle xSemaphoreCreateBinary failed!");
}
}
}
/**
* @details: This function is Uart2 TXDMA PDMA0 for RS485
*/
void UART2_TXDMA(uint32_t UART2_TXDMA_Trans_SrcAddr, uint32_t UART2_TXDMA_Trans_Count)
{
/* Open PDMA Channel 2 for UART2 TX */
PDMA_RESET(PDMA0,1 << 2);
PDMA_Open(PDMA0,1 << 2);
/* Select basic mode */
PDMA_SetTransferMode(PDMA0, 2, PDMA_UART2_TX, 0, 0);
/* Set data width and transfer count */
PDMA_SetTransferCnt(PDMA0, 2, PDMA_WIDTH_8, UART2_TXDMA_Trans_Count);
/* Set PDMA Transfer Address */
PDMA_SetTransferAddr(PDMA0, 2, UART2_TXDMA_Trans_SrcAddr, PDMA_SAR_INC, UART2_BASE, PDMA_DAR_FIX);
/* Select Single Request */
PDMA_SetBurstType(PDMA0, 2, PDMA_REQ_SINGLE, 0);
/* Set timeout */
PDMA_SetTimeOut(PDMA0, 2, UART2_TXDMA_Trans_TimeOutCnt_POWER, UART2_TXDMA_Trans_TimeOutCnt);//distable
/* NVIC IRQ */
PDMA_EnableInt(PDMA0,2, PDMA_INT_TRANS_DONE);
PDMA_EnableInt(PDMA0,3, PDMA_INT_TIMEOUT);
//NVIC_SetPriority(PDMA0_IRQn, 6);
NVIC_EnableIRQ(PDMA0_IRQn);
/* Enable UART2 PDMA TX */
UART_PDMA_ENABLE(UART2, UART_INTEN_TXPDMAEN_Msk);
}
/**
* @details: This function is Uart2 RXDMA PDMA0 for RS485
*/
void UART2_RXDMA(uint32_t UART2_RXDMA_Trans_DesAddr, uint32_t UART2_RXDMA_Trans_Count)
{
/* Open PDMA Channel 3 for UART2 RX */
PDMA_Open(PDMA0,1 << 3);
/* Select basic mode */
PDMA_SetTransferMode(PDMA0, 3, PDMA_UART2_RX, 0, 0);
/* Set data width and transfer count */
PDMA_SetTransferCnt(PDMA0, 3, PDMA_WIDTH_8, UART2_RXDMA_Trans_Count);
/* Set PDMA Transfer Address */
PDMA_SetTransferAddr(PDMA0,3, UART2_BASE, PDMA_SAR_FIX, UART2_RXDMA_Trans_DesAddr, PDMA_DAR_INC); //RX
/* Select Single Request */
PDMA_SetBurstType(PDMA0, 3, PDMA_REQ_SINGLE, 0);
/* Set timeout 000 = PDMA channel 3 time-out clock source is HCLK/2^8 200M/256 = 0.78125MHZ = 1.28us */
//PDMA0->TOUTPSC0_7 &= ~(0x03<<12);
PDMA_SetTimeOut(PDMA0, 3, UART2_RXDMA_Trans_TimeOutCnt_POWER, UART2_RXDMA_Trans_TimeOutCnt);//0x0E84 //PDMA_SetTimeOut(PDMA0, 3, UART2_RXDMA_Trans_TimeOutCnt_POWER, UART2_RXDMA_Trans_TimeOutCnt); //Enable 0x1E84
//PDMA_EnableTimeout(PDMA0,BIT3);
/* NVIC IRQ */
//PDMA_EnableInt(PDMA0, 2, PDMA_INT_TRANS_DONE);
PDMA_EnableInt(PDMA0, 3, PDMA_INT_TIMEOUT);
//NVIC_SetPriority(PDMA0_IRQn, 6);
NVIC_EnableIRQ(PDMA0_IRQn);
/* Enable UART2 PDMA RX */
UART_PDMA_ENABLE(UART2, UART_INTEN_RXPDMAEN_Msk);
}
/**
* @details: This function is DMA0 Init
*/
void DMA0_Init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
CLK_EnableModuleClock(PDMA0_MODULE);
NVIC_SetPriority(PDMA0_IRQn, 5);//NVIC_SetPriority(PDMA0_IRQn, 11);
/* Lock protected registers */
SYS_LockReg();
}
/**
* @details: This function is PDMA0 IRQHandler
*/
void PDMA0_IRQHandler(void)
{
uint32_t status = PDMA_GET_INT_STATUS(PDMA0);
/* abort PDMA0 IRQ error */
if(status & 0x1){
RS_LOGE("Abort PDMA0 interrupt error");
if(PDMA_GET_ABORT_STS(PDMA0) & 0x1){
RS_LOGE("Abort PDMA0 Chanel_0 interrupt error");
}else if(PDMA_GET_ABORT_STS(PDMA0) & 0x2){
RS_LOGE("Abort PDMA0 Chanel_1 interrupt error");
}else if(PDMA_GET_ABORT_STS(PDMA0) & 0x4){
RS_LOGE("Abort PDMA0 Chanel_2 interrupt error");
}else if(PDMA_GET_ABORT_STS(PDMA0) & 0x8){
RS_LOGE("Abort PDMA0 Chanel_3 interrupt error");
}
PDMA_CLR_ABORT_FLAG(PDMA0,PDMA_GET_ABORT_STS(PDMA0));
}else if(status & 0x2){ /* DMA Transfer Done */
if(PDMA_GET_TD_STS(PDMA0)&(1 << 0)){ /* uart1-tx */
/* Chanel_0 DMA Transfer Done */
/* Enable UART1 UART_INTEN_TXENDIEN_Msk UART FIFO IS empty? */
PDMA_CLR_TD_FLAG(PDMA0,PDMA_GET_TD_STS(PDMA0));
UART_ENABLE_INT(UART1, (UART_INTEN_TXENDIEN_Msk));
NVIC_SetPriority(UART1_IRQn, 6);
NVIC_EnableIRQ(UART1_IRQn);
}else if(PDMA_GET_TD_STS(PDMA0)&(1 << 1)){ /* uart1-rx */
/* Chanel_1 DMA Transfer Done */
}else if(PDMA_GET_TD_STS(PDMA0)&(1 << 2)){ /* uart2-tx */
/* Chanel_2 DMA Transfer Done */
PDMA_CLR_TD_FLAG(PDMA0,PDMA_GET_TD_STS(PDMA0));
UART_ENABLE_INT(UART2, (UART_INTEN_TXENDIEN_Msk));
NVIC_SetPriority(UART2_IRQn, 6);
NVIC_EnableIRQ(UART2_IRQn);
}else if(PDMA_GET_TD_STS(PDMA0)&(1 << 3)){ /* uart2-rx */
/* Chanel_3 DMA Transfer Done */
PDMA_CLR_TD_FLAG(PDMA0,PDMA_GET_TD_STS(PDMA0));
}else if(PDMA_GET_TD_STS(PDMA0)&(1 << 4)){ /* uart4-tx */
/* Chanel_4 DMA Transfer Done */
PDMA_CLR_TD_FLAG(PDMA0,PDMA_GET_TD_STS(PDMA0));
UART_ENABLE_INT(UART4, (UART_INTEN_TXENDIEN_Msk));
NVIC_SetPriority(UART4_IRQn, 6);
NVIC_EnableIRQ(UART4_IRQn);
}else if(PDMA_GET_TD_STS(PDMA0)&(1 << 5)){ /* uart4-rx */
PDMA_CLR_TD_FLAG(PDMA0,PDMA_GET_TD_STS(PDMA0));
/* Chanel_5 DMA Transfer Done */
}else if(PDMA_GET_TD_STS(PDMA0)&(1 << 6)){ /* uart5-tx */
PDMA_CLR_TD_FLAG(PDMA0,PDMA_GET_TD_STS(PDMA0));
/* Chanel_6 DMA Transfer Done */
UART_ENABLE_INT(UART5, (UART_INTEN_TXENDIEN_Msk));
NVIC_SetPriority(UART5_IRQn, 6);
NVIC_EnableIRQ(UART5_IRQn);
}else if(PDMA_GET_TD_STS(PDMA0)&(1 << 7)){ /* uart5-rx */
/* Chanel_7 DMA Transfer Done */
PDMA_CLR_TD_FLAG(PDMA0,PDMA_GET_TD_STS(PDMA0));
}
/* timeout */
}else if(status & (1<<8)){ /* uart1-tx */
/* Chanel_0 DMA Transfer Timeout */
PDMA_CLR_TMOUT_FLAG(PDMA0,0);
}else if(status & (1<<9)){ /* uart1-rx */
/* Chanel_1 DMA Recv Timeout */
PDMA_CLR_TMOUT_FLAG(PDMA0,1);
PDMA_SetTimeOut(PDMA0, 1, 0, 0);
BaseType_t pxHigherPriorityTaskWoken;
xSemaphoreGiveFromISR(UART1_Recv_Done_BinarySemHandle, &pxHigherPriorityTaskWoken);
}else if(status & (1<<10)){ /* uart2-tx */
/* Chanel_2 DMA Transfer Timeout */
PDMA_CLR_TMOUT_FLAG(PDMA0,2);
}else if(status & (1<<11)){ /* uart2-rx */
/* Chanel_3 DMA Recv Timeout */
PDMA_CLR_TMOUT_FLAG(PDMA0,3); ///////////////////////////////////////
PDMA_SetTimeOut(PDMA0, 3, 0, 0);
BaseType_t pxHigherPriorityTaskWoken;
xSemaphoreGiveFromISR(UART2_Recv_Done_BinarySemHandle, &pxHigherPriorityTaskWoken);
}else if(status & (1<<12)){ /* uart4-tx */
/* Chanel_4 DMA Transfer Timeout */
PDMA_CLR_TMOUT_FLAG(PDMA0,4);
}else if(status & (1<<13)){ /* uart4-rx 4G */
/* Chanel_5 DMA Recv Timeout */
PDMA_CLR_TMOUT_FLAG(PDMA0,5);
PDMA_SetTimeOut(PDMA0, 5, 0, 0);
BaseType_t pxHigherPriorityTaskWoken;
xSemaphoreGiveFromISR(UART4_Recv_Done_BinarySemHandle, &pxHigherPriorityTaskWoken);
}else if(status & (1<<14)){ /* uart5-tx */
/* Chanel_6 DMA Transfer Timeout */
PDMA_CLR_TMOUT_FLAG(PDMA0,6);
}else if(status & (1<<15)){ /* uart5-rx */
/* Chanel_7 DMA Recv Timeout */
PDMA_CLR_TMOUT_FLAG(PDMA0,7);
PDMA_SetTimeOut(PDMA0, 7, 0, 0);
BaseType_t pxHigherPriorityTaskWoken;
xSemaphoreGiveFromISR(UART5_Recv_Done_BinarySemHandle, &pxHigherPriorityTaskWoken);
}else{
RS_LOGW("PDMA0_IRQHandler unknown interrupt");
}
}
/**
* @details: This function is Uart2 RS485 IRQHandler
*/
void UART2_IRQHandler(void)
{
//RS_LOGD("UART2_IRQHandler ok\n");
uint32_t u32IntSts = UART2->INTSTS;
if(u32IntSts & UART_INTSTS_TXENDINT_Msk){
RS485_Channel2_Recv_EN();
BaseType_t xHigherPriorityTaskWoken;
xSemaphoreGiveFromISR(UART2_Transfer_Done_BinarySemHandle,&xHigherPriorityTaskWoken);
UART_DisableInt(UART2, (UART_INTEN_TXENDIEN_Msk));
NVIC_DisableIRQ(UART2_IRQn);
}
}
void RS485_2_Communication_Send_Recv_Pro(void)
{
/* Recv And Deal Data */
RS485_Channel2_Send_EN();
Send_Modbus_Que_t Send_Modbus_Que;
memset(&Send_Modbus_Que, 0, sizeof(Send_Modbus_Que));
if(xQueueReceive(RS485_2_Recv_Communication_Data_QueueHandle, &Send_Modbus_Que, portMAX_DELAY) == pdTRUE){
//Modbus-04-数据组包
memset(Func4_Send_Frame, 0, sizeof(Func4_Send_Frame));
Modbus_Rtu_Send_Func4_Pack(Send_Modbus_Que.Device_Addr_Data,
Send_Modbus_Que.Data_num_Addr,
Send_Modbus_Que.Data_Num,
Func4_Send_Frame
);
#if 1
//数据发送
UART2_TXDMA((uint32_t)Func4_Send_Frame, 8);
if(xSemaphoreTake(UART2_Transfer_Done_BinarySemHandle, (TickType_t)200) == pdTRUE){
//数据接收
memset(rs485_recvdata, 0, sizeof(rs485_recvdata));
UART2_RXDMA((uint32_t)rs485_recvdata, sizeof(rs485_recvdata));
if(xSemaphoreTake(UART2_Recv_Done_BinarySemHandle, (TickType_t)200) == pdTRUE){
//解析数据
memset(Para_Data, 0, sizeof(Para_Data));
if(Modbus_Rtu_Para_Func4_Pack(Send_Modbus_Que.Device_Addr_Data, Send_Modbus_Que.Data_Num, rs485_recvdata, Para_Data)==0){
//通过设备配置编号-更新链表数据
if(Bms_Config_Data_Update(Send_Modbus_Que.Device_Config_Num, Send_Modbus_Que.Data_num_Addr, Para_Data, Send_Modbus_Que.Data_Num*2, 2)==0){
xEventGroupSetBits(DEVICE_List_Data_Update_EventGroup_handle, 1<<(Send_Modbus_Que.Device_Config_Num-1));
}
}
}else{
RS_LOGD("UART2_Recv_Done_BinarySemHandle Timeout");
}
UART_PDMA_DISABLE(UART2, UART_INTEN_TXPDMAEN_Msk | UART_INTEN_RXPDMAEN_Msk);
delay_ms(20);
}
}
}
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待续。。。

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