PLL DLL

参考：高频电子线路-----张肃文     电子技术基础.模拟部分-----康华光

http://bbs.ednchina.com/BLOG_ARTICLE_1813834.HTM  （DLL & PLL）

http://baike.baidu.com/view/694181.htm?fr=aladdin （VCO）

DLL-Delay locked loop用在数字电路中，用来自动调节一路信号的延时，使两路信号的相位一致（边沿对齐），在需要某些数字信号（比如data bus上的信号）与系统时钟同步的情况下，DLL将两路clock的边沿对齐（实际上是使被调节的clock滞后系统clock 整数个周期），用被调节的clock做控制信号，就可以产生与系统时钟严格同步的信号（比如输出数据data跟输入clock同步，边沿的延时不受到电压、温度、频率影响）。

 

PLL--Phase locked loop除了用作相位跟踪（输出跟输入同频同相，这种情况下跟DLL有点相似）外，可以用来做频率综合（frequency synthesizer）， 输出频率稳定度跟高精度低漂移参考信号（比如温补晶振）几乎相当的高频信号，这时，它是一个频率源。利用PLL，可以方便地产生不同频率的高质量信号，PLL输出的信号抖动（频域上表现为相噪）跟它的环路带宽，鉴相频率大小有关。总的说来，PLL的环路带宽越小，鉴相频率越高，它的相位噪声越小（时域上抖动也越小）。 低通滤波器（环路滤波器一般为低通滤波器）可以滤除输入时钟的高频抖动，因此，PLL的输出时钟抖动主要来自于VCO本身和电源噪声，和输入信号没有关系。

 

http://www.google.com/patents/US6313615

It is sometimes desirable to run microprocessor cores at a very high frequency or a very low frequency. To do this, the microprocessor core voltage supply is increased accordingly. If the associated phase locked loop circuit is not designed to respond to a very wide range of core voltage supplies, the phase locked loop circuit may fail. One feature of the present invention makes phase locked loop circuits more robust. For example, aspects of the present invention reduce the risk of phase locked loop failures by maintaining a constant, regulated, and filtered voltage regardless of the increases in the microprocessor core voltage supply. Therefore, mobile personal computers, which tend to use very low power, benefit as well as high performance desktop computers.

The SFR enables the use of modem power management techniques. For example, when it is desired to change microprocessor core voltage and frequency at the same time, the SFR  allows one dimension that does not change. This dimension is the analog supply voltage.