(原創) 博客園正式支援Verilog語法著色功能 (SOC) (Verilog)

Abstract
以前在貼Verilog代碼時，都只能挑C++或者C#的語法著色，但兩者的keyword畢竟不太一樣， 透過dudu的幫助，我將Verilog 2001的keyword加上了，現在博客園也能漂亮的顯示Verilog代碼了!!

Introduction
以下是個典型的Verilog代碼，現在keyword都能正確顯示，真是太感動了...。

 module checksum_task_logic (
   input         clk,
   input         reset_n,
   input         go,
   input         data_in_ready,
   input  [31:0] data_to_process,
   output [15:0] result
 );
 
 reg        data_in_ready_delay;
 reg [31:0] data_in_reg;
 reg [31:0] sum_reg;
 
 wire [31:0] sum_1;
 wire [31:0] sum_2;
 wire [31:0] sum_3;
 wire [31:0] next_sum_reg;
 
 // first adder stage (16-bits) fold upper and lower half
 assign sum_1 = data_in_reg[31:16] + data_in_reg[15:0];
 
 // second adder state (32-bits) of sum_1 and previously stored sum (sum_reg)
 assign next_sum_reg = sum_1 + sum_reg;
 
 // Fold in upper (carry count) and lower half of sum register   
 assign sum_2 = sum_reg[31:16] + sum_reg[15:0];
 
 // Fold in upper (possible carry) and lower half of sum_2
 assign sum_3 = sum_2[31:16] + sum_2[15:0];
 
 // Invert the sum (one's complement) for result
 assign result = { ~(sum_3[15:0]) };
 
 // delay register for data_in_ready
 always@(posedge clk or negedge reset_n) begin
   if (reset_n == 1'b0)
     data_in_ready_delay <= 1'b0;
   else
     data_in_ready_delay <= data_in_ready;
 end // always@
 
 // Write to the data_in register
 always@(posedge clk or negedge reset_n) begin
   if (reset_n == 1'b0)
     data_in_reg <= 32'h00000000;
   else
     data_in_reg <= data_to_process;
 end // always@
 
 // Write to the sum register the next value
 always@(posedge clk or negedge reset_n) begin
   if (reset_n == 1'b0)
     sum_reg <= 32'h00000000;
   else if (go) // clears sum_reg at start of checksum calculation
     sum_reg <= 32'h0000_0000;
   else if (data_in_ready_delay == 1'b1)
     sum_reg <= next_sum_reg;
   else 
     sum_reg <= sum_reg;
 end // always@
 
 endmodule