用74HC163设计余3码计数器(结构描述)

题目：用VHDL层次结构设计方法设计程序并仿真（时序），底层器件是74HC163。

 

library ieee;         --第一个底层设计实体 nand_gate
use ieee.std_logic_1164.all;
entity nand_gate is
port( op1 , op2 : in std_logic;     --nand_gate的两个数据输入端
    nand_result : out std_logic);  --nand_gate的数据输出端口
end nand_gate;
architecture behave of nand_gate is
begin
    nand_result <= not (op1 and op2);  --nand_gate 的功能
end behave;

library ieee;        --第二个底层设计实体 not_gate
use ieee.std_logic_1164.all;
entity not_gate is
port(           op : in std_logic;  --not_gate 的数据输入端
        not_result : out std_logic);  --not_gate的数据输出端口
end not_gate;
architecture behave of not_gate is
begin
    not_result <= not op;      --not_gate 的功能
end behave;

library ieee;   --第三个底层设计实体
use ieee.std_logic_1164.all;
entity and_gate is
port( op1 , op2 : in std_logic;   --and_gate 的数据输入端
     and_result : out std_logic);   --and_gate的数据输出端口
end and_gate;
architecture behave of and_gate is
begin
    and_result <= op1 and op2;    --and_gate 的功能
end behave;

library ieee;               --第四个底层设计实体 74HC163
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity counter74163 is
port (ep , et , clk , ld , rd : in std_logic;  --控制端 et、ep，时钟信号clk，置数ld，复位rd
                            d : in unsigned(3 downto 0);    --数据输入端
                            q : out unsigned(3 downto 0);  --数据输出端
                            c : buffer std_logic);   --进位输出
end counter74163;
architecture behave of counter74163 is
signal iq : unsigned(3 downto 0);
begin
process(clk , ld , rd , ep , et , iq , d)
begin
    if(iq = 0) then iq <= d;
    elsif(clk'event and clk = '1') then
        if(rd = '0') then iq <= (others => '0');   --同步清零
        elsif(ld = '0') then iq <= d;             --同步置数
        elsif c = '1' then iq <= d;              --计数满，回d
        elsif (ep and et) = '1' then iq <= iq + 1;  --计数
        end if;
    end if;
    if(iq = 0) then iq <= d;
    elsif(iq = 13) and (et = '1') then c <= '1';    --产生进位输出
    else c <= '0';
    end if;
    q <= iq;
end process;
end behave;

library ieee;            --程序包
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
package lowgate_components is
component nand_gate       --说明原件与非门
    port( op1 , op2 : in std_logic;
        nand_result : out std_logic);
end component;
component not_gate    --说明原件非门
    port(       op : in std_logic;
         not_result : out std_logic);
end component;
component and_gate  --说明原件与门
    port( op1 , op2 : in std_logic;   
          and_result : out std_logic);
end component;
component counter74163    --说明原件74HC163
    port(ep , et , clk , ld , rd : in std_logic;
                            d    : in unsigned(3 downto 0);
                            q    : out unsigned(3 downto 0);
                            c    : buffer std_logic);
end component;
end lowgate_components;


library ieee;     --顶层设计实体
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.lowgate_components.all;
entity counter_excess_3_code is
port(Clk, Ep, Et, Ld : in std_logic;             --时钟信号，控制端，置数端
    D    : in unsigned(3 downto 0);    --数据输入端
    Iq   : buffer unsigned(3 downto 0);   --数据输出端
    rco  : out std_logic);       --进位输出端口
end counter_excess_3_code;
architecture behave of counter_excess_3_code is
signal b3 , b4: std_logic;
begin
G1 : counter74163 port map      --对74HC163的一次例化
        (et => Et , ep => Ep , clk => Clk , ld => b4 , rd => '1',
        d => D , q => Iq);
G2 : nand_gate port map    --对于非门的一次例化
        (op1 => Iq(3) , op2 => Iq(2) , nand_result => b3);
G3 : not_gate port map      --对非门的一次例化
        (op => b3 , not_result => rco);
G4 : and_gate port map   --对与门的一次例化2
        (op1 => b3 , op2 => Ld , and_result => b4);
end behave;