简易DDS发生器制作

简易DDS发生器制作

简介

  • ‌DDS 信号发生器‌是采用直接数字频率合成(Direct Digital Synthesis)技术的电子测量仪器,通过数字方式直接合成所需波形,具有‌频率分辨率高、切换速度快、相位连续‌等核心优势,广泛应用于通信、雷达、电子测量等领域 。‌

描述基本模块

相位累加器

module phase_adder12b(clk, rst_n, phase_step, phase_out, datinv);
	input clk, rst_n;
	input [7:0] phase_step;
	output reg [9:0] phase_out;
	output reg datinv;
	reg [11:0] cnt;
	always @(posedge clk or negedge rst_n)
		if(!rst_n)
			cnt <= 12'b0;
		else
			cnt <= cnt + phase_step;
	always @(cnt)
		case(cnt[11:10])
			2'b00: begin phase_out = cnt[9:0]; datinv = 0; end
			2'b01: begin phase_out = ~cnt[9:0]; datinv = 0; end
			2'b10: begin phase_out = cnt[9:0]; datinv = 1; end
			2'b11: begin phase_out = ~cnt[9:0]; datinv = 1; end
			default: begin phase_out = cnt[9:0]; datinv = 0; end
		endcase
		
endmodule

数据校正模块

module sin_dat_adj(
	input [7:0] din,
	input datflag,
	output wire [7:0] dout,
	output squ_out
);

assign squ_out = datflag;
assign dout = datflag? ~ din + 1 : din;

endmodule 

配置锁相环

  • 按照如下方式配置锁相环:
    img
    img
    img
    img
    img
    img

仅使用clk0,其余不用配置

img
img

配置ROM模块

配置文件

  • 将正弦波在一个周期内的数据记录为.mif格式
-- Copyright (C) 2018  Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Intel Program License 
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors.  Please
-- refer to the applicable agreement for further details.

-- Quartus Prime generated Memory Initialization File (.mif)

WIDTH=8;
DEPTH=1024;

ADDRESS_RADIX=UNS;
DATA_RADIX=HEX;

CONTENT BEGIN
	[0..2]  :   7F;
	[3..7]  :   80;
	[8..12]  :   81;
	[13..17]  :   82;
	[18..23]  :   83;
	[24..28]  :   84;
	[29..33]  :   85;
	[34..38]  :   86;
	[39..43]  :   87;
	[44..48]  :   88;
	[49..53]  :   89;
	[54..58]  :   8A;
	[59..64]  :   8B;
	[65..69]  :   8C;
	[70..74]  :   8D;
	[75..79]  :   8E;
	[80..84]  :   8F;
	[85..89]  :   90;
	[90..94]  :   91;
	[95..100]  :   92;
	[101..105]  :   93;
	[106..110]  :   94;
	[111..115]  :   95;
	[116..120]  :   96;
	[121..126]  :   97;
	[127..131]  :   98;
	[132..136]  :   99;
	[137..141]  :   9A;
	[142..146]  :   9B;
	[147..152]  :   9C;
	[153..157]  :   9D;
	[158..162]  :   9E;
	[163..168]  :   9F;
	[169..173]  :   A0;
	[174..178]  :   A1;
	[179..183]  :   A2;
	[184..189]  :   A3;
	[190..194]  :   A4;
	[195..199]  :   A5;
	[200..205]  :   A6;
	[206..210]  :   A7;
	[211..216]  :   A8;
	[217..221]  :   A9;
	[222..226]  :   AA;
	[227..232]  :   AB;
	[233..237]  :   AC;
	[238..243]  :   AD;
	[244..248]  :   AE;
	[249..254]  :   AF;
	[255..259]  :   B0;
	[260..265]  :   B1;
	[266..271]  :   B2;
	[272..276]  :   B3;
	[277..282]  :   B4;
	[283..287]  :   B5;
	[288..293]  :   B6;
	[294..299]  :   B7;
	[300..304]  :   B8;
	[305..310]  :   B9;
	[311..316]  :   BA;
	[317..322]  :   BB;
	[323..328]  :   BC;
	[329..333]  :   BD;
	[334..339]  :   BE;
	[340..345]  :   BF;
	[346..351]  :   C0;
	[352..357]  :   C1;
	[358..363]  :   C2;
	[364..369]  :   C3;
	[370..375]  :   C4;
	[376..381]  :   C5;
	[382..388]  :   C6;
	[389..394]  :   C7;
	[395..400]  :   C8;
	[401..406]  :   C9;
	[407..413]  :   CA;
	[414..419]  :   CB;
	[420..425]  :   CC;
	[426..432]  :   CD;
	[433..438]  :   CE;
	[439..445]  :   CF;
	[446..452]  :   D0;
	[453..458]  :   D1;
	[459..465]  :   D2;
	[466..472]  :   D3;
	[473..479]  :   D4;
	[480..486]  :   D5;
	[487..493]  :   D6;
	[494..500]  :   D7;
	[501..507]  :   D8;
	[508..514]  :   D9;
	[515..521]  :   DA;
	[522..529]  :   DB;
	[530..536]  :   DC;
	[537..544]  :   DD;
	[545..551]  :   DE;
	[552..559]  :   DF;
	[560..567]  :   E0;
	[568..575]  :   E1;
	[576..583]  :   E2;
	[584..591]  :   E3;
	[592..600]  :   E4;
	[601..608]  :   E5;
	[609..617]  :   E6;
	[618..626]  :   E7;
	[627..635]  :   E8;
	[636..644]  :   E9;
	[645..653]  :   EA;
	[654..663]  :   EB;
	[664..673]  :   EC;
	[674..683]  :   ED;
	[684..693]  :   EE;
	[694..704]  :   EF;
	[705..715]  :   F0;
	[716..727]  :   F1;
	[728..738]  :   F2;
	[739..751]  :   F3;
	[752..764]  :   F4;
	[765..777]  :   F5;
	[778..791]  :   F6;
	[792..806]  :   F7;
	[807..823]  :   F8;
	[824..840]  :   F9;
	[841..860]  :   FA;
	[861..882]  :   FB;
	[883..908]  :   FC;
	[909..942]  :   FD;
	[943..1023]  :   FE;
END;

配置ROM

  • 按照如下方式配置ROM
    img
    img
    img
  • 导入配置好的.mif文件,并设置为正弦波模式
    img
    img

拼接模块

  • verilog文件模块化后,按照如下方式进行拼接
    img

配置引脚

  • 根据开发板原理图,按照如下方式配置引脚
    img
  • 按照如下方式进行接线
    img

烧录与调试

  • 打开逻辑分析仪,调处如下界面
    img
  • 在空白处双击,调出节点查看器
    img
  • 选择以下节点
    img
  • 将时钟选择为OSC_50M
    img
  • 调到数据端,将正弦波输出改为"无符号线状图"
    img
  • 在逻辑分析仪配置后可看到正弦波图形
    img
posted @ 2026-04-14 21:43  奶龙大王  阅读(34)  评论(0)    收藏  举报