mengdie - 博客园

2015年4月27日

摘要： 1 quick and dirty = Done or constructed in ahasty,approximate,temporarilyadequatemanner, but notexact,fullyformed, orreliablefor a long period of ti... 阅读全文

posted @ 2015-04-27 19:29 mengdie 阅读(231) 评论(0) 推荐(0)

2015年4月24日

VHDL之conversion function

摘要： VHDL Type Cast and Conversion Functions **In ASIC design, do NEVER use integer or natural for signals, use conversion functions instead** The pictur... 阅读全文

posted @ 2015-04-24 22:20 mengdie 阅读(439) 评论(0) 推荐(0)

2015年4月18日

QS之warning message

摘要： Multiple message categories are specified as a comma separated list. 阅读全文

posted @ 2015-04-18 15:23 mengdie 阅读(125) 评论(0) 推荐(0)

2015年4月17日

Verilog之openMSP430(1)

摘要： openMSP430_IO interruptVerilog file: omsp_gpio.v 1 //============================================================================ 2 // 4) INTERRUPT GE... 阅读全文

posted @ 2015-04-17 19:49 mengdie 阅读(582) 评论(0) 推荐(0)

QS之vcom

摘要： -2008 | -2002 | -93 | -87 choose VHDL 2008, 2002, 1993, or 1987-explicit resolve ambiguous overloads-work specify work library-check_synthesis ... 阅读全文

posted @ 2015-04-17 17:23 mengdie 阅读(116) 评论(0) 推荐(0)

HDL之Bitwise operation

摘要： 1 Verilog1.1 Bitwise operator Bitwise operators perform a bit wise operation on two operands. They take each bit in one operand and perform the op... 阅读全文

posted @ 2015-04-17 17:17 mengdie 阅读(618) 评论(0) 推荐(0)

Embedded之memory type

摘要： 1 Types of memory 2 Characteristics 阅读全文

posted @ 2015-04-17 15:43 mengdie 阅读(177) 评论(0) 推荐(0)

2015年4月16日

RFID之UID

摘要： 1 Unique identifier (UID) The VICCs are uniquely identified by a 64 bits unique identifier (UID). This is used for addressing eachVICC uniquely and ... 阅读全文

posted @ 2015-04-16 23:43 mengdie 阅读(1607) 评论(0) 推荐(0)

VHDL之package

摘要： Pacakge Frequently used pieces of VHDL code are usually written in theform of COMPONENTS, FUNCTIONS, or PROCEDURES. Such codes are thenplaced insid... 阅读全文

posted @ 2015-04-16 20:07 mengdie 阅读(1815) 评论(0) 推荐(0)

QS之vsim

摘要： vsim -The vsim command invokes the VSIM simulator-L … (optional) Specifies the library to search for design units instantiated from Verilog and for ... 阅读全文

posted @ 2015-04-16 16:57 mengdie 阅读(358) 评论(0) 推荐(0)