此时仍相当于有个上升沿。初始值为4'b0000。`timescale 1ns / 1psmodule add( // inputs clk, // outputs sum );input wire clk;output reg [3:0] sum;initial begin sum = 0;endalways @ (posedge clk) begin sum = sum + 1;end endmodulemodule test_add();reg clk;wire [3:0] sum;always begin clk = 1; #1... Read More
posted @ 2011-08-22 20:41
露初晞
Views(420)
Comments(0)
Diggs(0)

浙公网安备 33010602011771号