verilog 时钟的0时刻

此时仍相当于有个上升沿。

初始值为4'b0000。

`timescale 1ns / 1ps

module add(
    // inputs
    clk,
    // outputs
    sum
    );

input wire clk;
output reg [3:0] sum;

initial begin
    sum = 0;
end

always @ (posedge clk) begin
    sum = sum + 1;
end
    
endmodule

module test_add();
reg clk;
wire [3:0] sum;

always begin
    clk = 1;
    #10;
    clk = 0;
    #10;
end

initial begin
    #1000 $stop;
end

add uut(clk, sum);

endmodule