露初晞

module divide_frequency( );reg clk;reg d_clk;reg [2:0] cnt;initial begin clk = 1; cnt = -1; d_clk = 1;endalways begin #10 clk = ~clk;endalways @ (clk) begin cnt = cnt + 1; if(cnt == 4) begin d_clk = ~d_clk; cnt = 0; endendalways @ (d_clk) begin $display("at time %t, ", $time, "d_clk = Read More