时钟分频

module divide_frequency(
    );
reg clk;
reg d_clk;

reg [2:0] cnt;

initial begin
    clk = 1;
    cnt = -1;
    d_clk = 1;
end

always begin
    #10 clk = ~clk;
end

always @ (clk) begin
    cnt = cnt + 1;
    if(cnt == 4) begin
        d_clk = ~d_clk;
        cnt = 0;
    end
end

always @ (d_clk) begin
    $display("at time %t, ", $time,
                    "d_clk = %b", d_clk
                );
end

endmodule

这是仿真代码，将20ns为周期的时钟放大4倍，变为80ns为周期的时钟。