【高速接口-RapidIO】5、Xilinx RapidIO核例子工程源码分析
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一、软件平台与硬件平台
软件平台：
操作系统：Windows 8.1 64-bit
开发套件：Vivado2015.4.2
硬件平台：
评估板：ZYNQ-7 ZC706 Evaluation Board
二、打开例子工程
1、新建工程，并在IP Catalog中找到Serial RapidIO Gen2
2、双击Serial RapidIO Gen2进入核的配置界面，所用参数全部保持默认，然后直接点击OK
3、在弹出的的对话框中直接点击Generate
4、在弹出的对话框中点击OK
5、等待srio_gen2_0核综合完毕，可能会花几分钟的时间
6、IP核综合完毕以后，单击srio_gen2_0，并点击鼠标右键，在弹出的菜单栏中单击Open IP Example Design…
7、在弹出的的对话框中选择例子工程的存放目录（这个目录可任意选择），然后单击OK
8、等一段时间以后例子工程就会自动打开
三、例子工程详解
3.1 工程概述
RapidIO核的例子工程的仿真顶层代码里面例化了两个实体，一个叫做srio_example_top_primary，另外一个叫做srio_example_top_mirror，如下图所示
其中每个例化实体都能被配置为发送支持的包类型，检测接收包失配以及上报链路的仿真细节。下表列出了例子工程中各个主要模块的功能简介
|
文件名 |
功能 |
|
srio_example_top.v |
例子工程的顶层模块 |
|
srio_request_gen.v |
生成请求事务的模块 |
|
instruction_list.vh |
这是一个Verilog头文件，里面定义了120个事务，它被包含在srio_request_gen.v模块中，srio_request_gen.v模块会把里面的所有事务依次发出去 |
|
srio_response_gen.v |
这个模块用来产生有响应事务的响应包 |
|
srio_condensed_gen.v |
当IP核的端口配置为Condensed I/O模式时，这个文件才会出现在例子工程中。它用来产生Condensed I/O模式的请求事务。 |
|
srio_quick_start.v |
这个模块与IP核的维护端口相连，用来发起维护事务。 |
|
maintenance_list.vh |
这是一个Verilog头文件，里面定义了一些维护事务，它被包含在srio_quick_start.v模块中，srio_quick_start.v模块会把里面的所有维护事务依次发出去用来配置相关寄存器 |
|
srio_report.v |
在仿真时，这个模块用来产生包接收和发送的时间戳，在硬件上运行的时候这个模块可以删除 |
|
srio_statistics.v |
这个模块用来收集核的统计信息并通过寄存器接口提交一些信息，提交的信息可以通过Vivado的调试特征以及用户设计来访问 |
|
srio_sim.v |
srio_sim.v是仿真顶层文件，它例化了两个核，分别是primary和mirror，并把它们连接到一起用于仿真。它也包含了上报测试是否成功的机制与超时（timeout）功能。 |
3.2 工程结构
例子工程的顶层模块例化了所有核的所有组件和在硬件上执行所需要的例子代码，整个工程的结构如下图所示。
整个结构包括时钟模块，复位模块，配置结构以及产生RapidIO事务的激励模块。
srio_quick_start模块在顶层srio_example_top.v中例化，它与IP核的维护端口相连用来产成维护事务，维护事务在maintenance_list.vh中进行定义，用户可以根据需要编辑maintenance_list.vh文件来添加，修改和移除维护事务。
srio_request_gen.v模块也在顶层srio_example_top.v中例化，它用来产生I/O事务与消息事务。这个模块也存储了期望的响应并把接收的响应与期望值进行比较。
srio_response_gen.v模块也在顶层srio_example_top.v中例化，它用来为接收到的请求事务生成对应的响应事务。
通过上图可以看出，产生I/O事务一共有两种方式：第一种是通过例子工程中自带的srio_request_gen.v产生I/O事务；第二种是通过顶层模块中Initiator和Target的resquest/response接口自己编写代码产生I/O事务。同理，产生维护事务也有两种方式：第一种是通过例子工程中自带的srio_quick_start.v模块产生维护事务；第二种是通过顶层模块中的维护接口自己编写代码产生维护事务。I/O事务的端口类型是AXI4-Stream类型，维护事务的端口类型是AXI4-Lite类型。
默认情况下，由于例子工程的顶层srio_example_top.v模块中，VALIDATION_FEATURES与QUICK_STARTUP两个参数均被设置为1，如下图所示
所以，例子工程是采用自带的srio_request_gen.v和srio_quick_start.v分别产生I/O事务与维护事务，另外，推荐注释掉外部接口以节省管脚和改善时序。
如果要使用外部接口产生I/O事务，那么需要设置参数VALIDATION_FEATURES=0，并且取消顶层模块srio_example_top.v中外部接口（axis_ireq_*,axis_tresp_*, axis_iresp_*, axis_treq_*, axis_iotx_*, axis_iorx_*）的注释。如果要使用外部接口产生维护事务，那些需要设置参数QUICK_STARTUP=0，并且取消顶层模块srio_example_top.v中外部接口（axis_maintr_*）的注释。使用外部接口的工程结构如下图所示
3.3 工程分析
I/O事务与维护事务
默认情况下，例子工程会使用srio_request_gen.v模块和srio_quick_start.v模块来产生I/O事务与维护事务。其中instruction_list.vh头文件定义了待发送的I/O事务，maintenance_list.vh头文件定义了待发送的维护事务。
当核被复位以后，maintenance_list.vh中的维护事务可以对核进行配置，维护事务可以在maintenance_list.vh进行添加、修改或移除。当没有处理器时，srio_quick_start.v模块可以用来管理公共的维护事务。当核复位以后，这是一种比较好的配置核的方法。
srio_request_gen.v模块和srio_response_gen.v模块可以用来产生I/O事务，srio_request_gen.v模块可以用来产生定义在instruction_list.vh中的I/O请求事务。instruction_list.vh中的I/O事务可以被添加、修改或移除，I/O事务的顺序是随机的，但是每次重新仿真时都是按照相同的顺序产生的。而且，只有IP核端口支持的事务才能被产生。srio_request_gen.v模块还可以追踪期望的响应并且比较接收的响应与期望值，这在仿真的时候可以很方便的确定事务的收发情况。
srio_response_gen.v模块用来产生接收到的请求所对应的目标响应I/O事务。如果写事务目标地址的第23位到16位为8’h12（address[23:16]=8’h12），那么数据负载会被存储在本地存储器。不需要响应的写事务会被丢弃，并且srio_response_gen.v模块不会响应SWRITE事务。如果读事务目标地址的第23位到16位为8’h12（address[23:16]=8’h12），那么数据将会从实际地址读出。对于那些地址不满足第23位到16位为8’h12（address[23:16]=8’h12）的事务，srio_response_gen.v模块将以地址递增的方式写入I/O事务携带的数据。响应会根据接收到的请求的顺序依次产生，所以不会有无序的事务产生。在所有的情况中，响应事务的优先级等于请求事务的优先级加1。
注意：每个srio_request_gen.v模块会消耗一个块RAM（Block RAM），每个srio_response_gen.v模块会消耗两个块RAM（Block RAM）。
配置结构
配置空间分布在RapidIO核的所有块中，配置结构的参考设计在例子设计的cfg_fabric模块中，用来管理每个块配置空间的访问情况。块（Block）的配置模块在配置总线（AXI4-Lite）上是作为从机存在的，cfg_fabric模块是作为主机存在的。维护事务的读写操作是从本地或者远程被发起，它是通过逻辑层的配置主端口接入配置模块，配置模块会把读写事务送入对应的块中，但如果地址不在各自配置寄存器的有效范围内，配置模块不会移交任何读写事务。往非法的空间写事务会被丢弃，读非法的空间将返回0。
时钟模块
例子设计的时钟模块与IP核的时钟模块是相同的。srio_clk模块有1个MMCM_ADV，1个IBUFDS和3个或4个BUFGs组成，在2x或4x模式，其中一个BUFGs将被转化为BUFGMUX。srio_clk模块会根据配置的不同产生合适的参考频率与用户时钟。
复位模块
srio_rst模块会把每个时钟域里面的异步复位信号转化为一个脉冲扩展的同步复位信号。当被用户设计调用的时候，srio_rst模块会用一个状态机强制对核重新初始化。
四、工程源码分析
3.1 顶层模块srio_example_top.v源码分析
顶层模块srio_example_top.v源码的端口定义如下
顶层模块包含5个参数：SIM_VERBOSE，VALIDATION_FEATURES，QUICK_STARTUP，STATISTICS_GATHERING和C_LINK_WIDTH。
SIM_VERBOSE设为1时，可以利用srio_report.v模块生成不可综合的报告。为0时，此功能被屏蔽。
VALIDATION_FEATURES设为1时，选择例子工程中的srio_request_gen.v和srio_response_gen.v产生相应的请求事务与响应事务对IP核的功能进行测试。为0时，选择外部的用户接口由用户自己编写请求事务与响应事务的代码对IP进行测试。
QUICK_STARTUP设为1时，选择例子工程中的srio_quick_start.v产生相应的维护事务对IP核的配置空间进行访问。为0时，选择外部的维护接口由用户自己编写维护事务的代码对IP核的配置空间进行访问。
STATISTICS_GATHERING设为1时，可以利用srio_statistics.v模块搜集IP的性能细节，这个模块是可综合的，可以通过Chipscope或ILA进行访问。为0时，此功能被屏蔽。
顶层模块的差分时钟sys_clkp和sys_clkn就是IP核配置界面第一页的参考时钟，由于例子工程中采用的全部是默认参数，所以这里这个时钟为125MHz，这个时钟可以由FPGA外部的有源晶振或锁相环芯片输出。
sys_rst为IP核的复位信号，高电平有效。
差分信号srio_rxn0和srio_rxp0为串行接收数据信号，srio_txn0和srio_txp0为串行发送数据信号。
sim_train_en信号是一个用来减少仿真时间的控制信号，仿真时把这个信号置1可以加快仿真速度，但是代码在硬件上运行时这个信号必须赋值为0。
led0是led指示信号，可以把port_initialized和link_initialized两个信号接到led0中，这样在硬件上执行时可以方便观察链路状态。
顶层模块srio_example_top.v中的第466行到第590行例化了RapidIO核，部分源码如下图所示
第612行到631行是例化了srio_report.v模块用来收集ireq接口的统计信息。除此以外，还例化了3个srio_report.v模块用来收集iresp，treq，tresp接口的统计信息。下图是收集ireq统计信息的源代码。源码如下图所示
第637行到684行srio_request_gen.v模块用来生成请求事务。这个模块有7个参数，分别为SEND_SWRITE，SEND_NWRITER，SEND_NWRITE，SEND_NREAD，SEND_FTYPE9，SEND_DB和SEND_MSG。当他们设置为1时，srio_request_gen.v模块将会把instruction_list.vh模块中对应的事务发送给SRIO IP核。部分源码如下图所示
第779行到804行例化了srio_response_gen.v模块，这个模块用来产生响应事务。部分源码如下图所示
第890行到937行例化了srio_quick_start.v模块，这个模块产生维护事务来访问配置空间。部分源码如下图所示
第944行到988行例化了srio_statistics.v模块，这个模块用来收集统计信息，它是一个可综合的模块。部分源码如下图所示
3.2 模块srio_request_gen.v源码分析
模块srio_request_gen.v的作用是产生RapidIO请求事务，上篇文章《Xilinx RapidIO核详解》（链接：https://www.cnblogs.com/liujinggang/p/10072115.html）已经提到过，RapidIO核为了简化包的构建过程，设计了一种精简的包格式——HELLO格式来完成包的构建，然后按照HELLO格式的时序把数据发送给RapidIO核，RapidIO核会把HELLO格式的包转化为标准的RapidIO串行物理层的包。这样，用户在设计请求事务的Verilog代码时只需要对HELLO格式的包与时序有所了解，而不需要过多的关注RapidIO的协议与RapidIO包格式。这里重新复习一下HELLO格式的包结构与HELLO格式的时序。
HELLO格式的包结构如下图所示：
HELLO格式的时序图如下图所示：
事实上，整个srio_request_gen.v源代码的核心就是先构建HELLO格式的包，然后把包头（Header）和数据按照HELLO格式的时序传给RapidIO核就可以了。下面详细分析一下。
分析instruction_list.vh头文件
在分析srio_request_gen.v源代码之前先来分析一下instruction_list.vh头文件。因为srio_request_gen.v文件中包含了instruction_list.vh头文件，instruction_list.vh头文件中定义了srio_request_gen.v将要发送的所有事务。
instruction_list.vh头文件的第1行到第9行定义了事务的个数以及所有事务的总个数，每种事务的个数由一个控制变量进行选择，源码如下：
第11行到50行是37个SWRITE事务（流写事务），其中第1列的12位数据是由8-bit的保留位（SWRITE事务没有srcTID字段），1-bit的保留位，2-bit的prio和1-bit的CRF组成，第2列是FTYPE字段，第3列是保留字段（SWRITE事务没有TTYPE字段），第4列的36-bit数据是由最高2-bit的保留位和34-bit的address字段组成，第5列是8-bit保留字段（SWRITE事务没有size字段），不管这个字段的值为多少，目标设备都会把这个值当做0来处理。源代码如下图所示
第52行到72行是19个NWRITE_R事务（带响应的写事务），其中第1列的12位数据是由8-bit的srcTID，1-bit的保留位，2-bit的prio和1-bit的CRF组成，第2列是FTYPE字段，第3列是TTYPE字段，第4列的36-bit数据是由最高2-bit的保留位和34-bit的address字段组成，第5列是size字段，这个字段的值为实际的数据量减1。比如size=0，表示实际传输的数据量为1。源代码如下图所示
第74行到94行是19个NWRITE事务（写事务），其中第1列的12位数据是由8-bit的srcTID，1-bit的保留位，2-bit的prio和1-bit的CRF组成，第2列是FTYPE字段，第3列是TTYPE字段，第4列的36-bit数据是由最高2-bit的保留位和34-bit的address字段组成，第5列是size字段，这个字段的值为实际的数据量减1。比如size=0，表示实际传输的数据量为1。源代码如下图所示
第96行到123行是26个NREAD事务（读事务），其中第1列的12位数据是由8-bit的srcTID，1-bit的保留位，2-bit的prio和1-bit的CRF组成，第2列是FTYPE字段，第3列是TTYPE字段，第4列的36-bit数据是由最高2-bit的保留位和34-bit的address字段组成，第5列是size字段，这个字段的值为实际的数据量减1。比如size=0，表示实际传输的数据量为1。源代码如下图所示
第125行到128行是两个DOORBELL事务（门铃事务），其中第1列的12位数据是由8-bit的srcTID，1-bit的保留位，2-bit的prio和1-bit的CRF组成，第2列是FTYPE字段，第3列是保留字段（DOORBELL事务没有TTYPE字段），第4列的36-bit数据是由最高4-bit的保留位，8-bit的信息高8位，8-bit的信息低8位以及最后的16-bit保留位组成。第5列是8-bit保留字段（DOORBELL事务没有size字段）。源代码如下图所示
第130行到148行是17个MESSAGE事务（消息事务），其中第1列的12位数据是由4-bit的msglen，4-bit的msgseg，1-bit的保留位，2-bit的prio和1-bit的CRF组成，第2列是FTYPE字段，第3列是保留字段（MESSAGE事务没有TTYPE字段），第4列的36-bit数据是由最高26-bit的保留位，6-bit的mailbox字段，2-bit的保留位以及2-bit的ltr组成。第5列是8-bit的size字段。源代码如下图所示
第150行到152行是1个Data Streaming事务，这是Xilinx定义的第9类事务，由于这种事务用的不多，我自己也不太了解，所以这里就不进行分析了。源代码如下图所示
分析srio_request_gen.v源码
在分析完毕instruction_list.vh头文件以后接下来开始着手分析srio_request_gen.v源码。分析过程中始终要记住的一点是：srio_request_gen.v的核心功能就是组装HELLO包头并把包头和数据按照HELLO格式的时序发送出去。
srio_request_gen.v源码的第50行到92行是参数与接口的定义。它包含7个参数，分别为SEND_SWRITE、SEND_NWRITER、SEND_NWRITE、SEND_NREAD、SEND_DB、SEND_FTYPE9和SEND_MSG，它们的默认值被设置为0，但是在顶层模块中例化的时候，它们的值分别被设置为1、1、1、1、0、1、1。如下图所示
根据上面分析instruction_list.vh头文件可知，如果上面的7个参数为1的话，各个事务的个数应该由instruction_list.vh头文件中NUM_SWRITES、NUM_NWRITERS、NUM_NWRITES、NUM_NREADS、NUM_DBS、NUM_MSGS和NUM_FTYPE9决定。
接下来就是端口的定义，其中log_clk与log_rst均由IP输出，log_clk的频率与链路线速率和链路宽度有关，具体的对应关系在上篇文章中能找到。接下来就是设备ID，目的ID以及源ID的定义。然后定义了ireq与iresp，它们都采用了AXI4-Stream协议。link_initialized信号由IP核输出，当它为高时表明链路成功初始化。以user_*开头的几个变量可以方便用户自定义HELLO格式包头中的各个字段。
第96到110行定义了HELLO格式包头中的FTYPE字段与TTYPE字段的值，这两个字段的值与事务的类型有关，源码如下图所示
第120行定义了一个memory类型变量，综合的时候ram的类型为分布式ram，121行导入了instruction_list.vh头文件，126行定义的变量可以看做AXI4-Stream总线上数据有效的标志位，当这个信号为高时，AXI4-Stream总线上tdata上的数据为有效数据。源代码如下图所示
第178行到205行用来初始化事务列表，instruction[ii]存放的是instruction_list.vh头文件中定义的各个事务的相关字段值，源代码如下图所示
第208到第219行是一些简单的赋值操作。其中第208行的val_ireq_tkeep和val_ireq_tuser是根据HELLO格式的时序要求赋值的，HELLO格式的时序要求tkeep为8’hFF，tuser在第一个有效的时钟（log_clk）周期内由src_id与dest_id拼接而成。第213行和第217行的go变量用来选择HELLO格式包头各个字段由用户定义还是由instruction_list.vh定义。第219行的header_beat变量就是HELLO格式的包头，在第一个有效时钟（log_clk）周期，tdata上的数据必须为header_beat。源代码如下图所示
第266行到288行主要用来产生有效时钟计数器current_beat_cnt与有效时钟计数总数number_of_data_beats。当AXI4_Stream总线的tvalid和tready信号同时为高时，时钟为有效时钟，current_beat_cnt加1，当检测到tlast信号为高时表明最后一个数据已发送完毕，所以把current_beat_cnt清0。由于tdata的宽度为64-bit，也就是8个字节，所以有效时钟计数总数number_of_data_beats为current_size右移3位。源代码如下图所示
第294行到306行用来产生AXI4_Stream总线中tlast信号，tlast为高时表明发送的是最后一个数据，所以tlast信号相当于一帧数据的边界。
第307行到328行用来产生AXI4_Stream总线中的tdata信号，当有效时钟计数器current_beat_cnt为0时，tdata为包头header_beat，包头header_beat后面是待发送的数据data_beat，例子工程为了简单起见，发送的数据是累加数，每个累加数为8-bit，然后把每个累加数拼接8次作为待发送的数据，也就是说，待发送的数据为64’h0000000000000000，64’h0101010101010101，64’h0202020202020202，……..，后面以此类推。
第330行到345行主要用来产生AXI4_Stream总线中的tvalid信号，同时也产生了一些其他的标志信号。至此，整个AXI4_Stream总线中的所有信号的逻辑都编写完毕，并且整个逻辑都是完全符合HELLO格式的时序。代码的核心部分全部分析完毕。
第351行到第371行与数据的存储相关。每当current_beat_cnt的值为0时，request_address变量加1， request_address也被赋给了tid，也就是说request_address也是事务ID值，同时request_address也是instruction的索引值。源代码如下图所示
第382行到第406行例化了一个RAMB36SDP原语，RAMB36SDP是一个大小为36Kb的简单双口Block RAM（SDP=Simple Dual Port）。它的作用是把请求事务的tid，current_ftype和current_size写入RAM中存起来，对于有响应的事务，RapidIO会收到一个响应事务，收到响应事务事务以后可以把存放在RAMB36SDP中的数据读出来与响应事务中对应的字段进行对比从而对整个事务的交互过程的正确性进行一个初步判断。关于RAMB36SDP原语的详细解释请阅读下一小节。源代码如下图所示
第458行到482行就是把存储在RAM中请求事务的tid，current_ftype和current_size与响应事务对应的字段进行对比，在仿真时给出对应的提示信息。
至此，整个产生请求事务的代码全部分析完毕，其他未分析到的代码大家自己尝试分析。
3.3 RAMB36SDP原语分析
RAMB36SDP是一个大小为36Kb的简单双口Block RAM（SDP=Simple Dual-Port），它其实是Virtex-5系列FPGA的一个原语，Vivado里面并没有RAMB36SDP的语法模板，ISE中才有它的语法模板，如下图所示
RAMB36SDP原语的完整代码如下所示
// RAMB36SDP : In order to incorporate this function into the design, // Verilog : the forllowing instance declaration needs to be placed // instance : in the body of the design code. The instance name // declaration : (RAMB36SDP_inst) and/or the port declarations within the // code : parenthesis may be changed to properly reference and // : connect this function to the design. All inputs // : and outputs must be connected. // <-----Cut code below this line----> // RAMB36SDP: 72x512 Simple Dual-Port BlockRAM w/ ECC // Virtex-5 // Xilinx HDL Language Template, version 14.7 RAMB36SDP #( .SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details .DO_REG(0), // Optional output register (0 or 1) .EN_ECC_READ("FALSE"), // Enable ECC decoder, "TRUE" or "FALSE" .EN_ECC_WRITE("FALSE"), // Enable ECC encoder, "TRUE" or "FALSE" .INIT(72'h000000000000000000), // Initial values on output port .SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY", // "GENERATE_X_ONLY" or "NONE" .SRVAL(72'h000000000000000000), // Set/Reset value for port output // The forllowing INIT_xx declarations specify the initial contents of the RAM .INIT_00(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_01(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_02(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_03(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_04(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_05(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_06(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_07(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_08(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_09(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_0A(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_0B(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_0C(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_0D(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_0E(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_0F(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_10(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_11(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_12(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_13(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_14(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_15(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_16(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_17(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_18(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_19(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_1A(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_1B(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_1C(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_1D(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_1E(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_1F(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_20(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_21(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_22(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_23(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_24(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_25(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_26(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_27(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_28(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_29(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_2A(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_2B(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_2C(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_2D(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_2E(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_2F(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_30(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_31(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_32(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_33(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_34(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_35(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_36(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_37(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_38(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_39(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_3A(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_3B(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_3C(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_3D(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_3E(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_3F(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_40(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_41(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_42(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_43(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_44(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_45(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_46(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_47(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_48(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_49(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_4A(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_4B(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_4C(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_4D(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_4E(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_4F(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_50(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_51(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_52(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_53(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_54(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_55(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_56(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_57(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_58(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_59(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_5A(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_5B(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_5C(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_5D(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_5E(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_5F(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_60(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_61(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_62(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_63(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_64(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_65(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_66(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_67(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_68(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_69(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_6A(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_6B(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_6C(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_6D(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_6E(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_6F(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_70(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_71(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_72(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_73(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_74(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_75(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_76(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_77(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_78(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_79(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_7A(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_7B(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_7C(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_7D(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_7E(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), .INIT_7F(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000), // The next set of INITP_xx are for the parity bits .INITP_00(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00), .INITP_01(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00), .INITP_02(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00), .INITP_03(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00), .INITP_04(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00), .INITP_05(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00), .INITP_06(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00), .INITP_07(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00), .INITP_08(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00), .INITP_09(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00), .INITP_0A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00), .INITP_0B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00), .INITP_0C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00), .INITP_0D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00), .INITP_0E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00), .INITP_0F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00) ) RAMB36SDP_inst ( .DBITERR(DBITERR), // 1-bit double bit error status output .SBITERR(SBITERR), // 1-bit single bit error status output .DO(DO), // 64-bit data output .DOP(DOP), // 8-bit parity data output .ECCPARITY(ECCPARITY), // 8-bit generated error correction parity .RDCLK(RDCLK), // 1-bit read port clock .RDEN(RDEN), // 1-bit read port enable .REGCE(REGCE), // 1-bit register enable input .SSR(SSR), // 1-bit synchronous output set/reset input .WRCLK(WRCLK), // 1-bit write port clock .WREN(WREN), // 1-bit write port enable .WRADDR(WRADDR), // 9-bit write port address input .RDADDR(RDADDR), // 9-bit read port address input .DI(DI), // 64-bit data input .DIP(DIP), // 8-bit parity data input .WE(WE) // 8-bit write enable input ); // End of RAMB36SDP_inst instantiation
每个36Kb简单双口块RAM（Simple dual-port block RAM）都能被配置为512x64（32Kb）大小的RAM和一个内置的汉明纠错编码（Hamming Error Correction）块，由于要用到汉明纠错编码，所以数据位宽需要多用到8-bit，这样数据位宽就被扩展到72-bit，当数据位宽为72-bit，深度为512时，RAM的大小刚好为36Kb（512 * 72 / 1024 = 36）,其中汉明纠错编码操作对用户是不可见的。每次写操作都会产生8-bit的保护位（原语中的ECCPARITY信号），这个8-bit的保护位在每次读操作的过程中可以用来纠正任何单比特的错误，或者检测（但不能纠正）任何双比特的错误。ECCPARITY输出信号没有可选的输出寄存器。原语中两个状态输出信号（SBITERR和DBITERR）的组合指示了三种可能的读操作结果：无错误（No Error），纠正了单比特错误（Signal Error Corrected）和检测到了双比特错误（Double Error Detected）。在读写操作的ECC（Error Correcting Code）模式均开启时（EN_ECC_READ = TRUE 并且 EN_ECC_WRITE = TRUE，EN_ECC_READ和EN_ECC_WRITE为原语的两个参数），读操作不能再存储器阵列中直接纠正错误，而只能把已经纠正完毕的数据输出给原语中的DO信号。ECC配置选项只有RAMB36SDP原语或FIFO36原语才支持。（此部分内容参考ug190的107页到155页）
Block RAM的ECC（Error Correcting Code）结构如下图所示
RAMB36SDP各个端口的定义如下表所示
|
端口名 |
方向 |
信号描述 |
|
DI[63:0] |
Input |
数据输入总线 |
|
DIP[7:0] |
Input |
数据输入奇偶校验总线 |
|
WRADDR[8:0] |
Input |
写地址总线 |
|
RDADDR[8:0] |
Input |
读地址总线 |
|
WREN |
Input |
写使能。当WREN=1时，数据将被写入存储器，当WREN=0，写操作不使能。 |
|
RDEN |
Input |
读使能。当RDEN=1时，数据将被从存储器读出，当RDEN=0，读操作不使能。 |
|
SSR |
Input |
同步设置/复位（Synchronous Set/Reset），这个信号用来复位输出寄存器的值为SRVAL，SRVAL是RAMB36SDP原语的一个参数。这个信号不会影响存储器存储单元的内容。 |
|
REGCE |
Input |
寄存器使能（Register Enable），端口输出寄存器使能信号。 |
|
WE[7:0] |
Input |
8位的字节写使能输入，由于输出数据总线为64-bit，一共为8个字节，所以字节写使能输入为8位，详细解释见表后的内容。 |
|
WRCLK |
Input |
写操作的时钟 |
|
RDCLK |
Input |
读操作的时钟 |
|
DO[63:0] |
Output |
数据输出总线 |
|
DOP[7:0] |
Output |
数据输出奇偶校验总线 |
|
SBITERR |
Output |
单比特错误（Signal Bit Error）状态 |
|
DBITERR |
Output |
双比特错误（Double Bit Error）状态 |
|
ECCPARITY |
Output |
ECC编码器输出数据总线 |
字节写使能（Byte-Writes）：（此部分内容参考pg058的第50页到51页）
当字节写使能功能打开时，WE总线的宽度为输入数据总线DI中包含的字节个数。例如，输入数据总线DI为64位，包含8个字节，所以WE总线的宽度为8。其中WE总线的最高位对于输入数据总线DI的最高位的字节，WE总线的最低位对于输入数据总线DI的最低位的字节，在写操作过程中，只有WE总线中为1的位对应的字节才能被写入存储器中，为0的位保持原来的值不变。
假设输入数据总线的宽度为24位，它包含3个字节，所以WE的宽度为3，下图是一个字节写使能开启时往RAM的0地址写入数据的时序图（假设RAM的初始值全部为0）
由上图可知，当WEA（也就是上文的WE）为3’b011时，DINA数据24’hFF EE DD的后两个字节会写入存储器的0地址，而存储器0地址的最高字节保持00不变，所以第一次写操作完毕以后存储器0地址的数据为24’h00 EE DD；当WEA（也就是上文的WE）为3’b010时，DINA数据24’hCC BB AA的中间那个字节BB会写入存储器的0地址，而存储器0地址的最高字节和最低字节则保持前一次的00和DD值不变，所以第二次写操作完毕以后存储器0地址的数据为24’h00 BB DD。后面几次操作依次类推即可。
3.4 模块srio_response_gen.v源码分析
模块srio_response_gen.v的作用是产生RapidIO响应事务。RapidIO协议中只有NREAD、DOORBELL、MESSAGE以及NWRITE_R这几种事务有响应事务。
srio_response_gen.v源码的第51行到72行定义了模块的端口。log_clk和log_rst分别为逻辑层时钟与复位，tresp和treq为两个AXI4-Stream通道，tresp是响应事务传输通道，treq是请求事务传输通道。源码如下图所示
第77行到90行定义了HELLO格式包头中的FTYPE字段与TTYPE字段的值，这两个字段的值与事务的类型有关，源码如下图所示
第99行到100行定义了AXI4-Stream总线上有效数据的标志，当tvalid和tready同时为高时，tdata上的数据为有效数据。源代码如下图所示
第161行到163行按照HELLO格式的时序要求，把tkeep信号赋值为8’hFF，把tuser信号由src_id和dest_id拼接而成，并在第一个有效时钟发出去。源代码如下图所示
第193行到203行用来产生HELLO时序中的tready。源代码如下图所示
第205行到220行用来产生treq通道第一拍的标志信号，并把tdata中的数据按照HELLO格式的定义把对应的关键字段剥离出来，值得注意的是第218行优先级字段prio为tdata重对应的字段加1，原因是响应事务的优先级为请求事务的优先级加1，上篇博客也提到过这一点。这部分源代码如下图所示
第224行到第235行用来生成有响应事务的标志，其中RapidiO协议中只有NREAD、DOORBELL、MESSAGE和NWRITE_R这几种事务有对应的响应事务。这部分源代码如下图所示
第240行到274行与本地数据的存储有关。其中第240行到250行的逻辑用来产生数据存取使能位data_store_wen，本文第3.3节提到过，只有地址字段的第23位到第16位为8’h12时，写事务的数据才能被存放到本地存储器，原因就是第243行的判断语句加上了这个判断。第252行到260行的逻辑用来产生数据存储的写地址信号data_store_waddr。第262行到274行的逻辑用来产生数据存储的读地址信号data_store_raddr。源代码如下图所示 
第276行到302行主要例化了一个RAMB36SDP用来存储写事务发送过来的数据。其中第276行用来产生数据存储的读使能标志。源代码如下图所示
第307行到第335行是把请求事务的包头（Header）信息存储在RAM中。其中第307行到308行把请求事务中HELLO格式定义的各个字段进行拼接作为RAM的输入，第325行到第335行用来产生RAM的读地址与写地址。
第337行例化了第二个Block RAM，它用来存储请求事务的HELLO格式信息。
第363行到第372行把从RAM中读出来的数据对应的字段剥离出来从而得到响应事务HELLO格式对应的字段。
第378行到第388行用来产生有效时钟的总数number_of_data_beats以及有效时钟计数器current_beat_cnt。这段逻辑与srio_request_gen.v中对应的逻辑完全一致。源代码如下图所示
第390行到400行用来产生tlast信号，发送最后一个数据时，tlast信号拉高。
第402行和第403行用来产生响应事务的包头（Header），第404行到414行用来产生响应事务的数据，其中响应事务的第一个有效时钟用来发送包头（Header），后面的有效时钟用来发送数据，这段逻辑也与srio_request_gen.v中对应的逻辑类似。源代码如下图所示
第459行到第469行用来产生AXI4-Stream中的tvalid信号，源代码如下
至此，整个响应事务的源代码分析完毕，其余未分析到的代码请自行分析。
3.5 模块srio_quick_start.v源码分析
模块srio_quick_start.v的作用是产生维护事务（Maintenance Transaction）访问本地设备和远程设备的配置空间。维护事务采用的接口协议为AXI4-Lite，它是一种轻量级的AXI4协议，有地址总线与数据总线，常用来实现单个寄存器的读写。在分析srio_quick_start.v源码之前首先分析一下maintenance_list.vh头文件。
分析maintenance_list.vh头文件
maintenance_list.vh头文件主要定义了维护事务相关的字段，其中第1列为2-bit的保留位，第2列为1-bit的远程/本地控制位，第3列为24-bit的地址，第4列为读/写控制位，第5列为32-bit的数据，第6列为4-bit的数据掩码（DATA MASK），部分源代码如下图所示
分析srio_quick_start.v源文件
srio_quick_start.v源文件的第68行到第101行是接口定义。log_clk和log_rst分别为逻辑层的时钟和复位。以maintr_*开头的信号为AXI4-Lite通道的信号，以user_*开头的信号是用户自定义的维护事务的相关字段，go变量用来在用户定义和maintenance_list.vh头文件定义的字段中进行选择
第105行到122行对maintenance_list.vh头文件中的参数进行了赋值，并引入了头文件，源代码如下图所示。
第192行到229行主要用来构建请求包，其本质就是产生AXI4-Lite的协议把数据发出去。部分源代码如下图所示
第233行到386行例化了一个RAMB36SDP原语，并用maintenance_list.vh头文件中定义的数据进行初始化。部分源代码如下图所示
第397行到416行主要负责响应侧的检测，通过maint_autocheck_error和maint_done指示检测状态。源代码如下图所示
至此，维护事务的代码分析完毕，它的代码逻辑相对来说比较简单。
另外，例子工程中还有两个模块srio_report.v和srio_statistics.v，它们只在仿真有用，在硬件上实现时最好删掉。这里不再作过多分析。只要理解了srio_request_gen.v与srio_response_gen.v，用RapidIO完成相关应用就足够了。
五、仿真
工程源码分析完毕以后，接下来就可以开始仿真了。例子工程中的代码一行都不要改，直接左键单击Run Simulation，在弹出的菜单中点击Run Behavioral Simulation，如下图所示
接着会出现下面的滚动框，在这个界面需要等待一会，如下图所示
上面的滚动框运行完毕以后就出现了波形界面，如下图所示
然后再点击下图中圈出的小图标把波形复位一下，如下图所示
复位波形以后在Tcl Console中输入指令：log_wave –r /* 。输入完毕以后按回车。这条指令的作用是记录所有中间变量的波形，这样后面要观察任何变量的波形只需要把它拖到波形界面中它的波形就会自动显示出来而不需要重新仿真，大大节约了时间。如下图所示
最后设置一个比较大的时间，我设置为10ms，然后点击它左边的按钮开始仿真，大约20分钟以后仿真会自动结束，如下图所示
仿真的过程中，在相应的时间点上，Tcl Console中会打印出包的收发情况
最后仿真结束以后，重新回到波形界面可以看到波形都正常产生了。这里最重要的两个信号就是link_initialized与port_initialized，当他们为高表示整个链路初始化完毕。至此，整个仿真过程全部结束，下篇文章会详细介绍每种事务的时序图以及需要注意的一些细节。
六、总结
本节主要分析了一下请求事务与响应事务的Verilog源码，事实上，它们的源码就是按照pg007_srio_gen2.pdf把HELLO格式与HELLO时序描述出来而已。当然官方的这套源码为了尽可能保证测试到核的所有功能，写的比较混乱，但在实际项目中可以充分借鉴它的设计思想，然后根据你自己的需求对不需要的地方进行修改来达到你的目标。除此以外，HELLO格式的时序其通过一个状态机来实现可能更加简洁易懂。总而言之，这套代码具有很大的参考价值，但是要想把这个核玩透还是得自己多在项目中理解。
下篇文章将会教大家如何在Vivado抓出每种事务的时序来对各种RapidIO的交互过程有一个更加清晰的理解。
七、附录
顶层模块srio_example_top_srio_gen2_0.v源码
1 // 2 // (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved. 3 // 4 // 5 // This file contains confidential and proprietary information 6 // of Xilinx, Inc. and is protected under U.S. and 7 // international copyright and other intellectual property 8 // laws. 9 // 10 // DISCLAIMER 11 // This disclaimer is not a license and does not grant any 12 // rights to the materials distributed herewith. Except as 13 // otherwise provided in a valid license issued to you by 14 // Xilinx, and to the maximum extent permitted by applicable 15 // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 // (2) Xilinx shall not be liable (whether in contract or tort, 21 // including negligence, or under any other theory of 22 // liability) for any loss or damage of any kind or nature 23 // related to, arising under or in connection with these 24 // materials, including for any direct, or any indirect, 25 // special, incidental, or consequential loss or damage 26 // (including loss of data, profits, goodwill, or any type of 27 // loss or damage suffered as a result of any action brought 28 // by a third party) even if such damage or loss was 29 // reasonably foreseeable or Xilinx had been advised of the 30 // possibility of the same. 31 // 32 // CRITICAL APPLICATIONS 33 // Xilinx products are not designed or intended to be fail- 34 // safe, or for use in any application requiring fail-safe 35 // performance, such as life-support or safety devices or 36 // systems, Class III medical devices, nuclear facilities, 37 // applications related to the deployment of airbags, or any 38 // other applications that could lead to death, personal 39 // injury, or severe property or environmental damage 40 // (individually and collectively, "Critical 41 // Applications"). Customer assumes the sole risk and 42 // liability of any use of Xilinx products in Critical 43 // Applications, subject only to applicable laws and 44 // regulations governing limitations on product liability. 45 // 46 // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 // PART OF THIS FILE AT ALL TIMES. 48 `timescale 1ps/1ps 49 (* DowngradeIPIdentifiedWarnings = "yes" *) 50 51 52 module srio_example_top_srio_gen2_0 #( 53 parameter SIM_VERBOSE = 1, // If set, generates unsynthesizable reporting 54 parameter VALIDATION_FEATURES = 1, // If set, uses internal instruction sequences for hw and sim test 55 parameter QUICK_STARTUP = 1, // If set, quick-launch configuration access is contained here 56 parameter STATISTICS_GATHERING = 1, // If set, I/O can be rerouted to the maint port [0,1] 57 parameter C_LINK_WIDTH = 1 58 ) 59 // port declarations ---------------- 60 ( 61 // Clocks and Resets 62 input sys_clkp, // MMCM reference clock 63 input sys_clkn, // MMCM reference clock 64 65 input sys_rst, // Global reset signal 66 67 // high-speed IO 68 input srio_rxn0, // Serial Receive Data 69 input srio_rxp0, // Serial Receive Data 70 71 72 73 output srio_txn0, // Serial Transmit Data 74 output srio_txp0, // Serial Transmit Data 75 76 77 78 input sim_train_en, // Set this only when simulating to reduce the size of counters 79 output [7:0] led0 80 81 ); 82 // ---------------------------------- 83 84 85 // wire declarations ---------------- 86 // 87 // ----------------------------------------------------------------------------- 88 // Note : Below portion of the wire declaration should be commented when 89 // used in non-shared mode AND the SRIO core 2nd instance is used to share 90 // common logic like clk, rst and GT Common with another instance of SRIO 91 // with Shared Logic (in DUT) option if the simulator throws errors. 92 // ----------------------------------------------------------------------------- 93 wire log_clk; 94 wire phy_clk; 95 wire gt_pcs_clk; 96 wire log_rst; 97 wire phy_rst; 98 wire clk_lock; // asserts from the MMCM 99 // 100 101 // signals into the DUT 102 103 104 wire ireq_tvalid; 105 wire ireq_tready; 106 wire ireq_tlast; 107 wire [63:0] ireq_tdata; 108 wire [7:0] ireq_tkeep; 109 wire [31:0] ireq_tuser; 110 111 wire iresp_tvalid; 112 wire iresp_tready; 113 wire iresp_tlast; 114 wire [63:0] iresp_tdata; 115 wire [7:0] iresp_tkeep; 116 wire [31:0] iresp_tuser; 117 118 wire treq_tvalid; 119 wire treq_tready; 120 wire treq_tlast; 121 wire [63:0] treq_tdata; 122 wire [7:0] treq_tkeep; 123 wire [31:0] treq_tuser; 124 125 wire tresp_tvalid; 126 wire tresp_tready; 127 wire tresp_tlast; 128 wire [63:0] tresp_tdata; 129 wire [7:0] tresp_tkeep; 130 wire [31:0] tresp_tuser; 131 132 wire maintr_rst = 1'b0; 133 134 wire maintr_awvalid; 135 wire maintr_awready; 136 wire [31:0] maintr_awaddr; 137 wire maintr_wvalid; 138 wire maintr_wready; 139 wire [31:0] maintr_wdata; 140 wire maintr_bvalid; 141 wire maintr_bready; 142 wire [1:0] maintr_bresp; 143 144 wire maintr_arvalid; 145 wire maintr_arready; 146 wire [31:0] maintr_araddr; 147 wire maintr_rvalid; 148 wire maintr_rready; 149 wire [31:0] maintr_rdata; 150 wire [1:0] maintr_rresp; 151 152 // signals from Validation modules 153 wire val_ireq_tvalid; 154 wire val_ireq_tready; 155 wire val_ireq_tlast; 156 wire [63:0] val_ireq_tdata; 157 wire [7:0] val_ireq_tkeep; 158 wire [31:0] val_ireq_tuser; 159 160 wire val_iresp_tvalid; 161 wire val_iresp_tready; 162 wire val_iresp_tlast; 163 wire [63:0] val_iresp_tdata; 164 wire [7:0] val_iresp_tkeep; 165 wire [31:0] val_iresp_tuser; 166 167 wire val_treq_tvalid; 168 wire val_treq_tready; 169 wire val_treq_tlast; 170 wire [63:0] val_treq_tdata; 171 wire [7:0] val_treq_tkeep; 172 wire [31:0] val_treq_tuser; 173 174 wire val_tresp_tvalid; 175 wire val_tresp_tready; 176 wire val_tresp_tlast; 177 wire [63:0] val_tresp_tdata; 178 wire [7:0] val_tresp_tkeep; 179 wire [31:0] val_tresp_tuser; 180 181 wire val_maintr_awvalid; 182 wire val_maintr_awready; 183 wire [31:0] val_maintr_awaddr; 184 wire val_maintr_wvalid; 185 wire val_maintr_wready; 186 wire [31:0] val_maintr_wdata; 187 wire val_maintr_bvalid; 188 wire val_maintr_bready; 189 wire [1:0] val_maintr_bresp; 190 191 wire val_maintr_arvalid; 192 wire val_maintr_arready; 193 wire [31:0] val_maintr_araddr; 194 wire val_maintr_rvalid; 195 wire val_maintr_rready; 196 wire [31:0] val_maintr_rdata; 197 wire [1:0] val_maintr_rresp; 198 199 200 //-- 201 //----------------------------------------------------------------------------// 202 203 204 //-- 205 206 // other core output signals that may be used by the user 207 wire [23:0] port_timeout; // Timeout value user can use to detect a lost packet 208 wire phy_rcvd_mce; // MCE control symbol received 209 (* mark_debug = "true" *) 210 wire phy_rcvd_link_reset; // Received 4 consecutive reset symbols 211 wire port_error; // In Port Error State 212 //(* mark_debug = "true" *)// this constraint is commented as it is failing due to new MLO flow 213 wire mode_1x; // Link is trained down to 1x mode 214 wire srio_host; // Endpoint is the system host 215 wire [223:0] phy_debug; // Useful debug signals 216 217 wire gtrx_disperr_or; // GT disparity error (reduce ORed) 218 219 wire gtrx_notintable_or; // GT not in table error (reduce ORed) 220 wire [15:0] deviceid; // Device ID 221 wire port_decode_error; // No valid output port for the RX transaction 222 (* mark_debug = "true" *) 223 wire idle_selected; // The IDLE sequence has been selected 224 (* mark_debug = "true" *) 225 wire idle2_selected; // The PHY is operating in IDLE2 mode 226 wire autocheck_error; // when set, packet didn't match expected 227 (* mark_debug = "true" *) 228 wire port_initialized; // Port is Initialized 229 (* mark_debug = "true" *) 230 wire link_initialized; // Link is Initialized 231 wire exercise_done; // sets when the generator(s) has completed 232 233 // other core output signals that may be used by the user 234 wire phy_mce = 1'b0; // Send MCE control symbol 235 wire phy_link_reset = 1'b0; // Send link reset control symbols 236 wire force_reinit = 1'b0; // Force reinitialization 237 238 239 // convert to ports when not using the pattern generator 240 241 242 wire axis_ireq_tvalid; 243 wire axis_ireq_tready; 244 wire axis_ireq_tlast; 245 wire [63:0] axis_ireq_tdata; 246 wire [7:0] axis_ireq_tkeep; 247 wire [31:0] axis_ireq_tuser; 248 249 wire axis_iresp_tvalid; 250 wire axis_iresp_tready; 251 wire axis_iresp_tlast; 252 wire [63:0] axis_iresp_tdata; 253 wire [7:0] axis_iresp_tkeep; 254 wire [31:0] axis_iresp_tuser; 255 256 wire axis_treq_tvalid; 257 wire axis_treq_tready; 258 wire axis_treq_tlast; 259 wire [63:0] axis_treq_tdata; 260 wire [7:0] axis_treq_tkeep; 261 wire [31:0] axis_treq_tuser; 262 263 wire axis_tresp_tvalid; 264 wire axis_tresp_tready; 265 wire axis_tresp_tlast; 266 wire [63:0] axis_tresp_tdata; 267 wire [7:0] axis_tresp_tkeep; 268 wire [31:0] axis_tresp_tuser; 269 270 wire axis_maintr_rst = 1'b0; 271 wire axis_maintr_awvalid = 1'b0; 272 wire axis_maintr_awready; 273 wire [31:0] axis_maintr_awaddr = 1'b0; 274 wire axis_maintr_wvalid = 1'b0; 275 wire axis_maintr_wready; 276 wire [31:0] axis_maintr_wdata = 1'b0; 277 wire [3:0] axis_maintr_wstrb = 1'b0; 278 wire axis_maintr_bvalid; 279 wire axis_maintr_bready = 1'b0; 280 wire [1:0] axis_maintr_bresp; 281 282 wire axis_maintr_arvalid = 1'b0; 283 wire axis_maintr_arready; 284 wire [31:0] axis_maintr_araddr = 1'b0; 285 wire axis_maintr_rvalid; 286 wire axis_maintr_rready = 1'b0; 287 wire [31:0] axis_maintr_rdata; 288 wire [1:0] axis_maintr_rresp; 289 290 wire ireq_autocheck_error; 291 wire ireq_request_done; 292 wire maint_autocheck_error; 293 wire maint_done; 294 295 // Vivado debug outputs for control of 296 (* mark_debug = "true" *) 297 wire peek_poke_go; 298 (* mark_debug = "true" *) 299 wire [23:0] user_addr; 300 (* mark_debug = "true" *) 301 wire [3:0] user_ftype; 302 (* mark_debug = "true" *) 303 wire [3:0] user_ttype; 304 (* mark_debug = "true" *) 305 wire [7:0] user_size; 306 (* mark_debug = "true" *) 307 wire [63:0] user_data; 308 (* mark_debug = "true" *) 309 wire [3:0] user_hop; 310 (* mark_debug = "true" *) 311 wire [15:0] dest_id; 312 (* mark_debug = "true" *) 313 wire [15:0] source_id; 314 (* mark_debug = "true" *) 315 wire id_override; 316 (* mark_debug = "true" *) 317 wire register_reset; 318 (* mark_debug = "true" *) 319 wire reset_all_registers; 320 (* mark_debug = "true" *) 321 wire [3:0] stats_address; 322 //(* mark_debug = "true" *) 323 // wire send_pna; 324 // (* mark_debug = "true" *) 325 // wire [2:0] sent_pna_cause_lsb; 326 // (* mark_debug = "true" *) 327 // wire in_recoverable_detect; 328 // (* mark_debug = "true" *) 329 // wire in_retry_detect; 330 // (* mark_debug = "true" *) 331 // wire out_recoverable_detect; 332 // (* mark_debug = "true" *) 333 // wire out_fatal_detect; 334 335 wire core_sent_pna; 336 337 wire core_received_pna; 338 339 wire core_sent_pr; 340 341 wire core_received_pr; 342 343 // Debug signals 344 wire go_req = peek_poke_go && user_ftype != 4'h8; 345 wire go_maint = peek_poke_go && user_ftype == 4'h8; 346 wire maint_inst = user_ttype == 4'h0; 347 reg [63:0] captured_data; 348 (* mark_debug = "true" *) 349 wire continuous_go; 350 reg continuous_go_q; 351 reg ireq_autocheck_error_q; 352 reg ireq_request_done_q; 353 reg reset_request_gen; 354 (* mark_debug = "true" *) 355 reg continuous_in_process; 356 reg reset_continuous_set; 357 (* mark_debug = "true" *) 358 reg stop_continuous_test; 359 reg [15:0] reset_continuous_srl; 360 wire [31:0] stats_data; 361 // }}} End wire declarations ------------ 362 363 364 // {{{ Drive LEDs to Development Board ------- 365 assign led0[0] = 1'b1; 366 assign led0[1] = 1'b1; 367 assign led0[2] = !mode_1x; 368 assign led0[3] = port_initialized; 369 assign led0[4] = link_initialized; 370 assign led0[5] = clk_lock; 371 assign led0[6] = sim_train_en ? autocheck_error : 1'b0; 372 assign led0[7] = sim_train_en ? exercise_done : 1'b0; 373 // }}} End LEDs to Development Board --------- 374 375 // assign send_pna = phy_debug[0]; 376 // assign sent_pna_cause_lsb = phy_debug[34:32]; 377 // assign in_recoverable_detect = phy_debug[40]; 378 // assign in_retry_detect = phy_debug[39]; 379 // assign out_recoverable_detect = phy_debug[38]; 380 // assign out_fatal_detect = phy_debug[37]; 381 // assign send_pna = phy_debug[0]; 382 assign core_sent_pna = phy_debug[160]; 383 assign core_received_pna = phy_debug[161]; 384 assign core_sent_pr = phy_debug[162]; 385 assign core_received_pr = phy_debug[163]; 386 387 388 389 390 assign continuous_go = 1'b0; 391 assign peek_poke_go = 1'b0; 392 assign user_addr = 24'b0; 393 assign user_ftype = 4'b0; 394 assign user_ttype = 4'b0; 395 assign user_size = 8'b0; 396 assign user_data = 64'b0; 397 assign user_hop = 4'b0; 398 assign dest_id = 16'b0; 399 assign source_id = 16'b0; 400 assign id_override = 1'b0; 401 assign register_reset = 1'b0; 402 assign reset_all_registers = 1'b0; 403 assign stats_address = 4'b0; 404 405 406 407 408 // feed back the last captured data to VIO 409 always @(posedge log_clk) begin 410 if (log_rst) begin 411 captured_data <= 64'h0; 412 // IO interface 413 end else if (iresp_tvalid && iresp_tready) begin 414 captured_data <= axis_iresp_tdata; 415 // maintenance interface 416 end else if (maintr_rvalid && maintr_rready) begin 417 captured_data <= axis_maintr_rdata; 418 end 419 end 420 421 // Continuous data flow 422 always @(posedge log_clk) begin 423 continuous_go_q <= continuous_go; 424 ireq_request_done_q <= ireq_request_done; 425 ireq_autocheck_error_q <= ireq_autocheck_error; 426 reset_request_gen <= sim_train_en ? log_rst : |reset_continuous_srl && continuous_in_process; 427 end 428 429 always @(posedge log_clk) begin 430 if (log_rst) begin 431 continuous_in_process <= 1'b0; 432 end else if (continuous_go && !continuous_go_q) begin 433 continuous_in_process <= 1'b1; 434 end else if (!continuous_go && continuous_go_q) begin 435 continuous_in_process <= 1'b0; 436 end 437 end 438 always @(posedge log_clk) begin 439 if (log_rst) begin 440 reset_continuous_set <= 1'b0; 441 stop_continuous_test <= 1'b0; 442 end else if (continuous_go && !continuous_go_q) begin 443 reset_continuous_set <= 1'b1; 444 stop_continuous_test <= 1'b0; 445 end else if (!ireq_autocheck_error_q && ireq_autocheck_error && continuous_in_process) begin 446 stop_continuous_test <= 1'b1; 447 end else if (!stop_continuous_test && !ireq_request_done_q && ireq_request_done && 448 continuous_in_process) begin 449 reset_continuous_set <= 1'b1; 450 end else begin 451 reset_continuous_set <= 1'b0; 452 end 453 end 454 always @(posedge log_clk) begin 455 if (log_rst) begin 456 reset_continuous_srl <= 16'h0; 457 end else if (reset_continuous_set) begin 458 reset_continuous_srl <= 16'hFFFF; 459 end else begin 460 reset_continuous_srl <= {reset_continuous_srl[14:0], 1'b0}; 461 end 462 end 463 464 // SRIO_DUT instantation ----------------- 465 // for production and shared logic in the core 466 srio_gen2_0 srio_gen2_0_inst 467 (//--------------------------------------------------------------- 468 .sys_clkp (sys_clkp ), 469 .sys_clkn (sys_clkn ), 470 .sys_rst (sys_rst ), 471 // all clocks as output in shared logic mode 472 .log_clk_out (log_clk ), 473 .phy_clk_out (phy_clk ), 474 .gt_clk_out (gt_clk ), 475 .gt_pcs_clk_out (gt_pcs_clk), 476 477 .drpclk_out (drpclk ), 478 479 .refclk_out (refclk ), 480 481 .clk_lock_out (clk_lock ), 482 // all resets as output in shared logic mode 483 .log_rst_out (log_rst ), 484 .phy_rst_out (phy_rst ), 485 .buf_rst_out (buf_rst ), 486 .cfg_rst_out (cfg_rst ), 487 .gt_pcs_rst_out (gt_pcs_rst), 488 489 //--------------------------------------------------------------- 490 491 .gt0_qpll_clk_out (gt0_qpll_clk_out ), 492 .gt0_qpll_out_refclk_out (gt0_qpll_out_refclk_out), 493 494 495 496 // //--------------------------------------------------------------- 497 .srio_rxn0 (srio_rxn0), 498 .srio_rxp0 (srio_rxp0), 499 500 .srio_txn0 (srio_txn0), 501 .srio_txp0 (srio_txp0), 502 503 .s_axis_ireq_tvalid (ireq_tvalid), 504 .s_axis_ireq_tready (ireq_tready), 505 .s_axis_ireq_tlast (ireq_tlast), 506 .s_axis_ireq_tdata (ireq_tdata), 507 .s_axis_ireq_tkeep (ireq_tkeep), 508 .s_axis_ireq_tuser (ireq_tuser), 509 510 .m_axis_iresp_tvalid (iresp_tvalid), 511 .m_axis_iresp_tready (iresp_tready), 512 .m_axis_iresp_tlast (iresp_tlast), 513 .m_axis_iresp_tdata (iresp_tdata), 514 .m_axis_iresp_tkeep (iresp_tkeep), 515 .m_axis_iresp_tuser (iresp_tuser), 516 517 .s_axis_tresp_tvalid (tresp_tvalid), 518 .s_axis_tresp_tready (tresp_tready), 519 .s_axis_tresp_tlast (tresp_tlast), 520 .s_axis_tresp_tdata (tresp_tdata), 521 .s_axis_tresp_tkeep (tresp_tkeep), 522 .s_axis_tresp_tuser (tresp_tuser), 523 524 .m_axis_treq_tvalid (treq_tvalid), 525 .m_axis_treq_tready (treq_tready), 526 .m_axis_treq_tlast (treq_tlast), 527 .m_axis_treq_tdata (treq_tdata), 528 .m_axis_treq_tkeep (treq_tkeep), 529 .m_axis_treq_tuser (treq_tuser), 530 531 .s_axi_maintr_rst (maintr_rst), 532 533 .s_axi_maintr_awvalid (maintr_awvalid), 534 .s_axi_maintr_awready (maintr_awready), 535 .s_axi_maintr_awaddr (maintr_awaddr), 536 .s_axi_maintr_wvalid (maintr_wvalid), 537 .s_axi_maintr_wready (maintr_wready), 538 .s_axi_maintr_wdata (maintr_wdata), 539 .s_axi_maintr_bvalid (maintr_bvalid), 540 .s_axi_maintr_bready (maintr_bready), 541 .s_axi_maintr_bresp (maintr_bresp), 542 543 .s_axi_maintr_arvalid (maintr_arvalid), 544 .s_axi_maintr_arready (maintr_arready), 545 .s_axi_maintr_araddr (maintr_araddr), 546 .s_axi_maintr_rvalid (maintr_rvalid), 547 .s_axi_maintr_rready (maintr_rready), 548 .s_axi_maintr_rdata (maintr_rdata), 549 .s_axi_maintr_rresp (maintr_rresp), 550 551 .sim_train_en (sim_train_en), 552 .phy_mce (phy_mce), 553 .phy_link_reset (phy_link_reset), 554 .force_reinit (force_reinit), 555 556 557 .phy_rcvd_mce (phy_rcvd_mce ), 558 .phy_rcvd_link_reset (phy_rcvd_link_reset), 559 .phy_debug (phy_debug ), 560 .gtrx_disperr_or (gtrx_disperr_or ), 561 .gtrx_notintable_or (gtrx_notintable_or ), 562 563 .port_error (port_error ), 564 .port_timeout (port_timeout ), 565 .srio_host (srio_host ), 566 .port_decode_error (port_decode_error ), 567 .deviceid (deviceid ), 568 .idle2_selected (idle2_selected ), 569 .phy_lcl_master_enable_out (), // these are side band output only signals 570 .buf_lcl_response_only_out (), 571 .buf_lcl_tx_flow_control_out (), 572 .buf_lcl_phy_buf_stat_out (), 573 .phy_lcl_phy_next_fm_out (), 574 .phy_lcl_phy_last_ack_out (), 575 .phy_lcl_phy_rewind_out (), 576 .phy_lcl_phy_rcvd_buf_stat_out (), 577 .phy_lcl_maint_only_out (), 578 //--- 579 580 581 582 583 584 //--- 585 .port_initialized (port_initialized ), 586 .link_initialized (link_initialized ), 587 .idle_selected (idle_selected ), 588 .mode_1x (mode_1x ) 589 ); 590 // End of SRIO_DUT instantiation --------- 591 592 593 // Initiator-driven side -------------------- 594 595 596 // {{{ IREQ Interface --------------------------- 597 // Select between internally-driven sequences or user sequences 598 assign ireq_tvalid = (VALIDATION_FEATURES) ? val_ireq_tvalid : axis_ireq_tvalid; 599 assign ireq_tlast = (VALIDATION_FEATURES) ? val_ireq_tlast : axis_ireq_tlast; 600 assign ireq_tdata = (VALIDATION_FEATURES) ? val_ireq_tdata : axis_ireq_tdata; 601 assign ireq_tkeep = (VALIDATION_FEATURES) ? val_ireq_tkeep : axis_ireq_tkeep; 602 assign ireq_tuser = (VALIDATION_FEATURES) ? val_ireq_tuser : axis_ireq_tuser; 603 604 assign axis_ireq_tready = (!VALIDATION_FEATURES) && ireq_tready; 605 assign val_ireq_tready = (VALIDATION_FEATURES) && ireq_tready; 606 607 608 609 610 // When enabled, report results. 611 // This is a simulation-only option and cannot be synthesized 612 generate if (SIM_VERBOSE) begin: ireq_reporting_gen 613 srio_report 614 #(.VERBOSITY (2), 615 .DIRECTION (1), 616 .NAME (0)) // Data is flowing into the core 617 srio_ireq_report_inst 618 ( 619 .log_clk (log_clk), 620 .log_rst (log_rst), 621 622 .tvalid (ireq_tvalid), 623 .tready (ireq_tready), 624 .tlast (ireq_tlast), 625 .tdata (ireq_tdata), 626 .tkeep (ireq_tkeep), 627 .tuser (ireq_tuser) 628 ); 629 end 630 endgenerate 631 // }}} End of IREQ Interface -------------------- 632 633 634 // {{{ Initiator Generator/Checker -------------- 635 636 // If internally-driven sequences are required 637 generate if (VALIDATION_FEATURES) begin: ireq_validation_gen 638 srio_request_gen_srio_gen2_0 639 #(.SEND_SWRITE (1), 640 .SEND_NWRITER (1), 641 .SEND_NWRITE (1), 642 .SEND_NREAD (1), 643 .SEND_FTYPE9 (0), 644 .SEND_DB (1), 645 .SEND_MSG (1)) 646 srio_request_gen_inst ( 647 .log_clk (log_clk), 648 .log_rst (reset_request_gen), 649 650 .deviceid (deviceid), 651 .dest_id (dest_id), 652 .source_id (source_id), 653 .id_override (id_override), 654 655 .val_ireq_tvalid (val_ireq_tvalid), 656 .val_ireq_tready (val_ireq_tready), 657 .val_ireq_tlast (val_ireq_tlast), 658 .val_ireq_tdata (val_ireq_tdata), 659 .val_ireq_tkeep (val_ireq_tkeep), 660 .val_ireq_tuser (val_ireq_tuser), 661 662 .val_iresp_tvalid (val_iresp_tvalid), 663 .val_iresp_tready (val_iresp_tready), 664 .val_iresp_tlast (val_iresp_tlast), 665 .val_iresp_tdata (val_iresp_tdata), 666 .val_iresp_tkeep (val_iresp_tkeep), 667 .val_iresp_tuser (val_iresp_tuser), 668 669 .link_initialized (link_initialized), 670 671 // use these ports to peek/poke IO transactions 672 .go (go_req), 673 .user_addr ({10'h000, user_addr}), 674 .user_ftype (user_ftype), 675 .user_ttype (user_ttype), 676 .user_size (user_size), 677 .user_data (user_data), 678 679 .request_autocheck_error (ireq_autocheck_error), 680 .request_done (ireq_request_done) 681 ); 682 end 683 endgenerate 684 // }}} End of Initiator Generator/Checker ------- 685 686 687 // {{{ IRESP Interface -------------------------- 688 // Select between internally-driven sequences or user sequences 689 690 assign iresp_tready = (VALIDATION_FEATURES) ? val_iresp_tready : axis_iresp_tready; 691 692 assign val_iresp_tvalid = (VALIDATION_FEATURES) && iresp_tvalid; 693 assign val_iresp_tlast = iresp_tlast; 694 assign val_iresp_tdata = iresp_tdata; 695 assign val_iresp_tkeep = iresp_tkeep; 696 assign val_iresp_tuser = iresp_tuser; 697 698 assign axis_iresp_tvalid = (!VALIDATION_FEATURES) && iresp_tvalid; 699 assign axis_iresp_tlast = iresp_tlast; 700 assign axis_iresp_tdata = iresp_tdata; 701 assign axis_iresp_tkeep = iresp_tkeep; 702 assign axis_iresp_tuser = iresp_tuser; 703 704 705 // When enabled, report results. 706 // This is a simulation-only option and cannot be synthesized 707 generate if (SIM_VERBOSE) begin: iresp_reporting_gen 708 srio_report 709 #(.VERBOSITY (2), 710 .DIRECTION (0), 711 .NAME (1)) // Data is flowing out of the core 712 srio_iresp_report_inst 713 ( 714 .log_clk (log_clk), 715 .log_rst (log_rst), 716 717 .tvalid (iresp_tvalid), 718 .tready (iresp_tready), 719 .tlast (iresp_tlast), 720 .tdata (iresp_tdata), 721 .tkeep (iresp_tkeep), 722 .tuser (iresp_tuser) 723 ); 724 end 725 endgenerate 726 // }}} End of IRESP Interface ------------------- 727 728 729 730 731 732 assign autocheck_error = ireq_autocheck_error || maint_autocheck_error; 733 assign exercise_done = ireq_request_done && maint_done; 734 735 // }}} End of Initiator-driven side ------------- 736 737 738 // {{{ Target-driven side ----------------------- 739 740 // {{{ TRESP Interface -------------------------- 741 // Select between internally-driven sequences or user sequences 742 assign tresp_tvalid = (VALIDATION_FEATURES) ? val_tresp_tvalid : axis_tresp_tvalid; 743 assign tresp_tlast = (VALIDATION_FEATURES) ? val_tresp_tlast : axis_tresp_tlast; 744 assign tresp_tdata = (VALIDATION_FEATURES) ? val_tresp_tdata : axis_tresp_tdata; 745 assign tresp_tkeep = (VALIDATION_FEATURES) ? val_tresp_tkeep : axis_tresp_tkeep; 746 assign tresp_tuser = (VALIDATION_FEATURES) ? val_tresp_tuser : axis_tresp_tuser; 747 748 assign axis_tresp_tready = (!VALIDATION_FEATURES) && tresp_tready; 749 assign val_tresp_tready = (VALIDATION_FEATURES) && tresp_tready; 750 751 752 // When enabled, report results. 753 // This is a simulation-only option and cannot be synthesized 754 generate if (SIM_VERBOSE) begin: tresp_reporting_gen 755 srio_report 756 #(.VERBOSITY (2), 757 .DIRECTION (1), 758 .NAME (8)) // Data is flowing into the core 759 srio_tresp_report_inst 760 ( 761 .log_clk (log_clk), 762 .log_rst (log_rst), 763 764 .tvalid (tresp_tvalid), 765 .tready (tresp_tready), 766 .tlast (tresp_tlast), 767 .tdata (tresp_tdata), 768 .tkeep (tresp_tkeep), 769 .tuser (tresp_tuser) 770 ); 771 end 772 endgenerate 773 // }}} End of TRESP Interface ------------------- 774 775 776 // {{{ Target Generator/Checker ----------------- 777 778 // If internally-driven sequences are required 779 generate if (VALIDATION_FEATURES) begin: tresp_validation_gen 780 srio_response_gen_srio_gen2_0 srio_response_gen_inst ( 781 .log_clk (log_clk), 782 .log_rst (log_rst), 783 784 .deviceid (deviceid), 785 .source_id (source_id), 786 .id_override (id_override), 787 788 .val_tresp_tvalid (val_tresp_tvalid), 789 .val_tresp_tready (val_tresp_tready), 790 .val_tresp_tlast (val_tresp_tlast), 791 .val_tresp_tdata (val_tresp_tdata), 792 .val_tresp_tkeep (val_tresp_tkeep), 793 .val_tresp_tuser (val_tresp_tuser), 794 795 .val_treq_tvalid (val_treq_tvalid), 796 .val_treq_tready (val_treq_tready), 797 .val_treq_tlast (val_treq_tlast), 798 .val_treq_tdata (val_treq_tdata), 799 .val_treq_tkeep (val_treq_tkeep), 800 .val_treq_tuser (val_treq_tuser) 801 ); 802 end 803 endgenerate 804 // }}} End of Target Generator/Checker ---------- 805 806 807 // {{{ TREQ Interface --------------------------- 808 // Select between internally-driven sequences or user sequences 809 810 assign treq_tready = (VALIDATION_FEATURES) ? val_treq_tready : axis_treq_tready; 811 812 assign val_treq_tvalid = (VALIDATION_FEATURES) && treq_tvalid; 813 assign val_treq_tlast = treq_tlast; 814 assign val_treq_tdata = treq_tdata; 815 assign val_treq_tkeep = treq_tkeep; 816 assign val_treq_tuser = treq_tuser; 817 818 assign axis_treq_tvalid = (!VALIDATION_FEATURES) && treq_tvalid; 819 assign axis_treq_tlast = treq_tlast; 820 assign axis_treq_tdata = treq_tdata; 821 assign axis_treq_tkeep = treq_tkeep; 822 assign axis_treq_tuser = treq_tuser; 823 824 825 // When enabled, report results. 826 // This is a simulation-only option and cannot be synthesized 827 generate if (SIM_VERBOSE) begin: treq_reporting_gen 828 srio_report 829 #(.VERBOSITY (2), 830 .DIRECTION (0), 831 .NAME (9)) // Data is flowing out of the core 832 srio_treq_report_inst 833 ( 834 .log_clk (log_clk), 835 .log_rst (log_rst), 836 837 .tvalid (treq_tvalid), 838 .tready (treq_tready), 839 .tlast (treq_tlast), 840 .tdata (treq_tdata), 841 .tkeep (treq_tkeep), 842 .tuser (treq_tuser) 843 ); 844 end 845 endgenerate 846 // }}} End of TREQ Interface -------------------- 847 848 849 850 851 852 // }}} End of Target-driven side ---------------- 853 854 // {{{ Maintenance Interface -------------------- 855 856 // Select between internally-driven sequences or user sequences 857 assign maintr_awvalid = (QUICK_STARTUP) ? val_maintr_awvalid : axis_maintr_awvalid; 858 assign maintr_awaddr = (QUICK_STARTUP) ? val_maintr_awaddr : axis_maintr_awaddr; 859 assign maintr_wvalid = (QUICK_STARTUP) ? val_maintr_wvalid : axis_maintr_wvalid; 860 assign maintr_wdata = (QUICK_STARTUP) ? val_maintr_wdata : axis_maintr_wdata; 861 assign maintr_bready = (QUICK_STARTUP) ? val_maintr_bready : axis_maintr_bready; 862 863 assign maintr_arvalid = (QUICK_STARTUP) ? val_maintr_arvalid : axis_maintr_arvalid; 864 assign maintr_araddr = (QUICK_STARTUP) ? val_maintr_araddr : axis_maintr_araddr; 865 assign maintr_rready = (QUICK_STARTUP) ? val_maintr_rready : axis_maintr_rready; 866 867 868 assign axis_maintr_awready = (!QUICK_STARTUP) && maintr_awready; 869 assign axis_maintr_wready = (!QUICK_STARTUP) && maintr_wready; 870 assign axis_maintr_bvalid = (!QUICK_STARTUP) && maintr_bvalid; 871 assign axis_maintr_bresp = maintr_bresp; 872 873 assign axis_maintr_arready = (!QUICK_STARTUP) && maintr_arready; 874 assign axis_maintr_rvalid = (!QUICK_STARTUP) && maintr_rvalid; 875 assign axis_maintr_rdata = maintr_rdata; 876 assign axis_maintr_rresp = maintr_rresp; 877 878 assign val_maintr_awready = (QUICK_STARTUP) && maintr_awready; 879 assign val_maintr_wready = (QUICK_STARTUP) && maintr_wready; 880 assign val_maintr_bvalid = (QUICK_STARTUP) && maintr_bvalid; 881 assign val_maintr_bresp = maintr_bresp; 882 883 assign val_maintr_arready = (QUICK_STARTUP) && maintr_arready; 884 assign val_maintr_rvalid = (QUICK_STARTUP) && maintr_rvalid; 885 assign val_maintr_rdata = maintr_rdata; 886 assign val_maintr_rresp = maintr_rresp; 887 888 889 // If internally-driven sequences are required 890 generate if (QUICK_STARTUP) begin: quick_maint_gen 891 srio_quick_start_srio_gen2_0 srio_quick_start_inst ( 892 .log_clk (log_clk), 893 .log_rst (log_rst), 894 895 .maintr_awvalid (val_maintr_awvalid), 896 .maintr_awready (val_maintr_awready), 897 .maintr_awaddr (val_maintr_awaddr), 898 .maintr_wvalid (val_maintr_wvalid), 899 .maintr_wready (val_maintr_wready), 900 .maintr_wdata (val_maintr_wdata), 901 .maintr_bvalid (val_maintr_bvalid), 902 .maintr_bready (val_maintr_bready), 903 .maintr_bresp (val_maintr_bresp), 904 905 .maintr_arvalid (val_maintr_arvalid), 906 .maintr_arready (val_maintr_arready), 907 .maintr_araddr (val_maintr_araddr), 908 .maintr_rvalid (val_maintr_rvalid), 909 .maintr_rready (val_maintr_rready), 910 .maintr_rdata (val_maintr_rdata), 911 .maintr_rresp (val_maintr_rresp), 912 913 // use these ports to peek/poke maintenance transactions 914 .go (go_maint), 915 .user_hop (user_hop), 916 .user_inst (maint_inst), 917 .user_addr (user_addr), 918 .user_data (user_data[31:0]), 919 920 .link_initialized (link_initialized), 921 .maint_done (maint_done), 922 .maint_autocheck_error (maint_autocheck_error) 923 ); 924 end else begin : no_quick_maint_gen 925 assign maintr_awaddr = 32'h0; 926 assign maintr_wvalid = 1'b0; 927 assign maintr_wdata = 32'h0; 928 assign maintr_bready = 1'b0; 929 assign maintr_arvalid = 1'b0; 930 assign maintr_araddr = 32'h0; 931 assign maintr_rready = 1'b0; 932 assign maint_done = 1'b1; 933 assign maint_autocheck_error = 1'b0; 934 end 935 endgenerate 936 937 // }}} End of Maintenance Interface ------------- 938 939 940 // {{{ Statistics Gatherer ---------------------- 941 942 // When enabled, statistics gatherer collects details about performance. 943 // This module is synthesizable and may be accessed through Chipscope 944 generate if (STATISTICS_GATHERING) begin: stats_gen 945 srio_statistics_srio_gen2_0 srio_statistics_inst ( 946 .log_clk (log_clk), 947 .phy_clk (phy_clk), 948 .gt_pcs_clk (gt_pcs_clk), 949 .log_rst (log_rst), 950 .phy_rst (phy_rst), 951 952 // outgoing port 1 953 .tvalid_o1 (ireq_tvalid), 954 .tready_o1 (ireq_tready), 955 .tlast_o1 (ireq_tlast), 956 .tdata_o1 (ireq_tdata), 957 958 // outgoing port 2 959 .tvalid_o2 (iresp_tvalid), 960 .tready_o2 (iresp_tready), 961 .tlast_o2 (iresp_tlast), 962 .tdata_o2 (iresp_tdata), 963 964 // incoming port 1 965 .tvalid_i1 (treq_tvalid), 966 .tready_i1 (treq_tready), 967 .tlast_i1 (treq_tlast), 968 .tdata_i1 (treq_tdata), 969 970 // incoming port 2 971 .tvalid_i2 (tresp_tvalid), 972 .tready_i2 (tresp_tready), 973 .tlast_i2 (tresp_tlast), 974 .tdata_i2 (tresp_tdata), 975 976 .link_initialized (link_initialized), 977 .phy_debug (phy_debug), 978 .gtrx_disperr_or (gtrx_disperr_or), 979 .gtrx_notintable_or (gtrx_notintable_or), 980 981 .register_reset (register_reset), 982 .reset_all_registers (reset_all_registers), 983 .stats_address (stats_address), 984 985 .stats_data (stats_data) 986 ); 987 end 988 endgenerate 989 990 // }}} End of Statistics Gatherer --------------- 991 992 endmodule
srio_request_gen_srio_gen2_0.v源码
1 // 2 // (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved. 3 // 4 // 5 // This file contains confidential and proprietary information 6 // of Xilinx, Inc. and is protected under U.S. and 7 // international copyright and other intellectual property 8 // laws. 9 // 10 // DISCLAIMER 11 // This disclaimer is not a license and does not grant any 12 // rights to the materials distributed herewith. Except as 13 // otherwise provided in a valid license issued to you by 14 // Xilinx, and to the maximum extent permitted by applicable 15 // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 // (2) Xilinx shall not be liable (whether in contract or tort, 21 // including negligence, or under any other theory of 22 // liability) for any loss or damage of any kind or nature 23 // related to, arising under or in connection with these 24 // materials, including for any direct, or any indirect, 25 // special, incidental, or consequential loss or damage 26 // (including loss of data, profits, goodwill, or any type of 27 // loss or damage suffered as a result of any action brought 28 // by a third party) even if such damage or loss was 29 // reasonably foreseeable or Xilinx had been advised of the 30 // possibility of the same. 31 // 32 // CRITICAL APPLICATIONS 33 // Xilinx products are not designed or intended to be fail- 34 // safe, or for use in any application requiring fail-safe 35 // performance, such as life-support or safety devices or 36 // systems, Class III medical devices, nuclear facilities, 37 // applications related to the deployment of airbags, or any 38 // other applications that could lead to death, personal 39 // injury, or severe property or environmental damage 40 // (individually and collectively, "Critical 41 // Applications"). Customer assumes the sole risk and 42 // liability of any use of Xilinx products in Critical 43 // Applications, subject only to applicable laws and 44 // regulations governing limitations on product liability. 45 // 46 // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 // PART OF THIS FILE AT ALL TIMES. 48 `timescale 1ps/1ps 49 50 module srio_request_gen_srio_gen2_0 51 #( 52 parameter SEND_SWRITE = 0, 53 parameter SEND_NWRITER = 0, 54 parameter SEND_NWRITE = 0, 55 parameter SEND_NREAD = 0, 56 parameter SEND_DB = 0, 57 parameter SEND_FTYPE9 = 0, 58 parameter SEND_MSG = 0) 59 ( 60 input log_clk, 61 input log_rst, 62 63 input [15:0] deviceid, 64 input [15:0] dest_id, 65 input [15:0] source_id, 66 input id_override, 67 68 output reg val_ireq_tvalid, 69 input val_ireq_tready, 70 output reg val_ireq_tlast, 71 output reg [63:0] val_ireq_tdata, 72 output [7:0] val_ireq_tkeep, 73 output [31:0] val_ireq_tuser, 74 75 input val_iresp_tvalid, 76 output reg val_iresp_tready, 77 input val_iresp_tlast, 78 input [63:0] val_iresp_tdata, 79 input [7:0] val_iresp_tkeep, 80 input [31:0] val_iresp_tuser, 81 82 input link_initialized, 83 input go, 84 input [33:0] user_addr, 85 input [3:0] user_ftype, 86 input [3:0] user_ttype, 87 input [7:0] user_size, 88 input [63:0] user_data, 89 90 output reg request_autocheck_error, 91 output reg request_done 92 ); 93 94 // {{{ local parameters ----------------- 95 96 localparam [3:0] NREAD = 4'h2; 97 localparam [3:0] NWRITE = 4'h5; 98 localparam [3:0] SWRITE = 4'h6; 99 localparam [3:0] DOORB = 4'hA; 100 localparam [3:0] MESSG = 4'hB; 101 localparam [3:0] RESP = 4'hD; 102 localparam [3:0] FTYPE9 = 4'h9; 103 104 localparam [3:0] TNWR = 4'h4; 105 localparam [3:0] TNWR_R = 4'h5; 106 localparam [3:0] TNRD = 4'h4; 107 108 localparam [3:0] TNDATA = 4'h0; 109 localparam [3:0] MSGRSP = 4'h1; 110 localparam [3:0] TWDATA = 4'h8; 111 112 // }}} End local parameters ------------- 113 114 115 // {{{ wire declarations ---------------- 116 reg [15:0] log_rst_shift; 117 wire log_rst_q = log_rst_shift[15]; 118 119 //synthesis attribute ram_style of instruction is distributed 120 wire [63:0] instruction [0:511]; 121 `include "instruction_list.vh" 122 123 reg [12:0] link_initialized_cnt; 124 wire link_initialized_delay = link_initialized_cnt[12]; 125 126 wire ireq_advance_condition = val_ireq_tready && val_ireq_tvalid; 127 wire iresp_advance_condition = val_iresp_tready && val_iresp_tvalid; 128 129 // request side 130 wire [63:0] request_data_out; 131 reg [47:0] request_data_out_q; // upper 63:48 unused 132 reg auto_advance_data; 133 reg [8:0] request_address; 134 135 wire [15:0] src_id; 136 wire [1:0] prio; 137 wire [7:0] tid; 138 wire [35:0] srio_addr; 139 wire [63:0] header_beat; 140 141 wire [3:0] current_ftype; 142 wire [3:0] current_ttype; 143 wire [7:0] current_size; 144 wire [15:0] current_size_ftype9; 145 wire [4:0] number_of_data_beats; 146 wire [12:0] number_of_data_beats_ftype9; 147 reg [4:0] number_of_data_beats_q; 148 reg [12:0] number_of_data_beats_q_ftype9; 149 reg [5:0] current_beat_cnt; 150 reg [13:0] current_beat_cnt_ftype9; 151 152 reg last_packet_beat_q, last_packet_beat_qq, last_packet_beat_qqq; 153 reg [7:0] data_beat, data_beat_q; 154 reg [15:0] instruction_cnt; 155 reg sent_all_packets; 156 157 reg go_q; 158 159 // response check side 160 reg expecting_a_response; 161 reg [8:0] write_queue_addr; 162 reg [8:0] read_queue_addr; 163 wire [63:0] write_queue_data_d; 164 reg [63:0] write_queue_data; 165 wire [63:0] read_queue_data; 166 reg [63:0] read_queue_data_q; 167 reg compare_received; 168 wire [3:0] expected_ftype; 169 wire [7:0] expected_tid; 170 wire [7:0] expected_size; 171 reg delay_assert_tready; 172 173 // }}} End wire declarations ------------ 174 175 176 // {{{ Common-use Signals --------------- 177 // Initialize instruction list 178 genvar ii; 179 generate 180 for (ii = 0; ii < 512; ii = ii + 1) begin : instruction_gen 181 // Load SWRITEs 182 if(ii < NUM_SWRITES) begin 183 assign instruction[ii] = swrite_instruction[(ii+1)*64-1:ii*64]; 184 // Load NWRITE_Rs 185 end else if(ii < (NUM_SWRITES + NUM_NWRITERS)) begin 186 assign instruction[ii] = nwriter_instruction[(ii-NUM_SWRITES+1)*64-1:(ii-NUM_SWRITES)*64]; 187 // Load NWRITEs 188 end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES)) begin 189 assign instruction[ii] = nwrite_instruction[(ii-NUM_SWRITES-NUM_NWRITERS+1)*64-1:(ii-NUM_SWRITES-NUM_NWRITERS)*64]; 190 // Load NREADs 191 end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS)) begin 192 assign instruction[ii] = nread_instruction[(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES+1)*64-1:(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES)*64]; 193 // Load DBs 194 end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS + NUM_DBS)) begin 195 assign instruction[ii] = db_instruction[(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS+1)*64-1:(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS)*64]; 196 // Load MSGs 197 end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS + NUM_DBS + NUM_MSGS)) begin 198 assign instruction[ii] = msg_instruction[(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS-NUM_DBS+1)*64-1:(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS-NUM_DBS)*64]; 199 end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS + NUM_DBS + NUM_MSGS + NUM_FTYPE9)) begin 200 assign instruction[ii] = ftype9_instruction[(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS-NUM_DBS-NUM_MSGS+1)*64-1:(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS-NUM_DBS-NUM_MSGS)*64]; 201 end else begin 202 assign instruction[ii] = 64'h0; 203 end 204 end 205 endgenerate 206 207 // Simple Assignments 208 assign val_ireq_tkeep = 8'hFF; 209 assign src_id = id_override ? source_id : deviceid; 210 assign prio = 2'h1; 211 assign val_ireq_tuser = {src_id, dest_id}; 212 assign tid = request_address[7:0]; 213 assign srio_addr = go ? user_addr : request_data_out_q[43:8]; 214 assign current_ftype = go ? user_ftype : request_data_out[51:48]; 215 assign current_ttype = go ? user_ttype : request_data_out_q[47:44]; 216 assign current_size = go ? user_size : request_data_out_q[7:0]; 217 assign current_size_ftype9 = go ? {user_size,user_size} : request_data_out_q[23:8]; 218 // //Fixed CR# 799600, 12/15/2014, Added ftype switch for message in below header in place of plain "tid" field. 219 assign header_beat = {((current_ftype == MESSG)? request_data_out[59:52] : tid), current_ftype, current_ttype, 1'b0, prio, 1'b0, current_size, srio_addr}; 220 // End Simple Assignments 221 222 always @(posedge log_clk or posedge log_rst) begin 223 if (log_rst) 224 log_rst_shift <= 16'hFFFF; 225 else 226 log_rst_shift <= {log_rst_shift[14:0], 1'b0}; 227 end 228 229 always @(posedge log_clk) begin 230 if (log_rst_q) begin 231 last_packet_beat_q <= 1'b1; 232 last_packet_beat_qq <= 1'b1; 233 last_packet_beat_qqq <= 1'b1; 234 number_of_data_beats_q <= 5'h0; 235 number_of_data_beats_q_ftype9 <= 13'h0; 236 read_queue_data_q <= 64'h0; 237 go_q <= 1'b0; 238 end else begin 239 last_packet_beat_q <= ireq_advance_condition && val_ireq_tlast; 240 last_packet_beat_qq <= last_packet_beat_q; 241 last_packet_beat_qqq <= last_packet_beat_qq || !link_initialized_delay; 242 number_of_data_beats_q <= number_of_data_beats; 243 number_of_data_beats_q_ftype9 <= number_of_data_beats_ftype9; 244 read_queue_data_q <= read_queue_data; 245 go_q <= go; 246 end 247 end 248 249 250 // put a sufficient delay on the initialization to improve simulation time. 251 // Not needed for actual hardware but does no damage if kept. 252 always @(posedge log_clk) begin 253 if (log_rst_q) begin 254 link_initialized_cnt <= 0; 255 end else if (link_initialized && !link_initialized_delay) begin 256 link_initialized_cnt <= link_initialized_cnt + 1'b1; 257 end else if (!link_initialized) begin 258 link_initialized_cnt <= 0; 259 end 260 end 261 262 // }}} End Common-use Signals ----------- 263 264 265 // {{{ Request Packet Formatter --------- 266 assign number_of_data_beats = current_beat_cnt == 0 ? current_size[7:3] : number_of_data_beats_q; 267 268 assign number_of_data_beats_ftype9 = current_beat_cnt_ftype9 == 0 ? current_size_ftype9[15:3] : number_of_data_beats_q_ftype9; 269 270 always @(posedge log_clk) begin 271 if (log_rst_q) begin 272 current_beat_cnt <= 6'h0; 273 end else if (ireq_advance_condition && val_ireq_tlast) begin 274 current_beat_cnt <= 6'h0; 275 end else if (ireq_advance_condition) begin 276 current_beat_cnt <= current_beat_cnt + 1'b1; 277 end 278 end 279 280 always @(posedge log_clk) begin 281 if (log_rst_q) begin 282 current_beat_cnt_ftype9 <= 14'h000; 283 end else if (ireq_advance_condition && val_ireq_tlast) begin 284 current_beat_cnt_ftype9 <= 14'h000; 285 end else if (ireq_advance_condition) begin 286 current_beat_cnt_ftype9 <= current_beat_cnt_ftype9 + 1'b1; 287 end 288 end 289 290 wire [13:0] extended_number_of_data_beats_ftype9; 291 292 assign extended_number_of_data_beats_ftype9 = {1'b0, number_of_data_beats_ftype9}; 293 294 always @(posedge log_clk) begin 295 if (log_rst_q) begin 296 val_ireq_tlast <= 1'b0; 297 end else if (((current_ftype == NREAD) || (current_ftype == DOORB)) && current_beat_cnt == 6'h00) begin 298 val_ireq_tlast <= !(ireq_advance_condition && val_ireq_tlast); 299 end else if ((current_beat_cnt == {1'b0, number_of_data_beats} && ireq_advance_condition && (current_ftype != FTYPE9)) || ((current_beat_cnt_ftype9 == extended_number_of_data_beats_ftype9) && ireq_advance_condition && (current_ftype == FTYPE9) )) begin 300 val_ireq_tlast <= !val_ireq_tlast; 301 end else if (!val_ireq_tready) begin 302 val_ireq_tlast <= val_ireq_tlast; 303 end else if (val_ireq_tready || !val_ireq_tvalid) begin 304 val_ireq_tlast <= 1'b0; 305 end 306 end 307 always @(posedge log_clk) begin 308 if ((current_beat_cnt == 0 && !ireq_advance_condition && (current_ftype != FTYPE9)) || (current_beat_cnt_ftype9 == 0 && !ireq_advance_condition && (current_ftype == FTYPE9))) begin 309 val_ireq_tdata <= header_beat; 310 end else if (go) begin 311 val_ireq_tdata <= user_data; 312 end else begin 313 val_ireq_tdata <= {8{data_beat}}; 314 end 315 end 316 always @* begin 317 data_beat = data_beat_q; 318 if (ireq_advance_condition && current_beat_cnt != 0) begin 319 data_beat = data_beat_q + 1'b1; 320 end 321 end 322 always @(posedge log_clk) begin 323 if (log_rst_q) begin 324 data_beat_q <= 8'h00; 325 end else begin 326 data_beat_q <= data_beat; 327 end 328 end 329 330 always @(posedge log_clk) begin 331 if (log_rst_q) begin 332 val_ireq_tvalid <= 1'b0; 333 instruction_cnt <= 16'h0; 334 sent_all_packets <= 1'b0; 335 end else if (link_initialized_delay && instruction_cnt < NUMBER_OF_INSTRUCTIONS && last_packet_beat_qqq) begin 336 val_ireq_tvalid <= 1'b1; 337 end else if (ireq_advance_condition && val_ireq_tlast) begin 338 val_ireq_tvalid <= 1'b0; 339 instruction_cnt <= instruction_cnt + 1'b1; 340 end else if (go && !go_q) begin 341 val_ireq_tvalid <= 1'b1; 342 end else if (instruction_cnt == NUMBER_OF_INSTRUCTIONS) begin 343 sent_all_packets <= 1'b1; 344 end 345 end 346 347 // }}} End Request Packet Formatter ----- 348 349 350 // {{{ Request Data Storage ------------- 351 always @(posedge log_clk) begin 352 if (log_rst_q) begin 353 request_address <= 9'h0; 354 end else if ((ireq_advance_condition && current_beat_cnt == 0 && (current_ftype != FTYPE9)) || ((current_beat_cnt_ftype9 == extended_number_of_data_beats_ftype9) && ireq_advance_condition && (current_ftype == FTYPE9))) begin 355 request_address <= request_address + 1'b1; 356 end 357 end 358 359 assign request_data_out = instruction[request_address]; 360 361 always @ (posedge log_clk) begin 362 if (ireq_advance_condition || auto_advance_data || last_packet_beat_qq) 363 request_data_out_q <= request_data_out[47:0]; 364 end 365 always @ (posedge log_clk) begin 366 if (log_rst_q) begin 367 auto_advance_data <= 1'b1; 368 end else if (ireq_advance_condition) begin 369 auto_advance_data <= 1'b0; 370 end 371 end 372 // }}} End of Request Data Storage ------ 373 374 375 // {{{ Response Queue ------------------- 376 377 assign write_queue_data_d = {44'h0, tid, current_ftype, current_size}; 378 always @ (posedge log_clk) begin 379 write_queue_data <= write_queue_data_d; 380 end 381 382 RAMB36SDP #( 383 .SIM_COLLISION_CHECK("NONE"), 384 .EN_ECC_READ("FALSE"), 385 .EN_ECC_WRITE("FALSE") 386 ) 387 response_queue_inst ( 388 .DI (write_queue_data), 389 .DIP (8'h0), 390 .RDADDR (read_queue_addr), 391 .RDCLK (log_clk), 392 .RDEN (1'b1), 393 .REGCE (1'b1), 394 .SSR (log_rst), 395 .WE ({8{expecting_a_response}}), 396 .WRADDR (write_queue_addr), 397 .WRCLK (log_clk), 398 .WREN (expecting_a_response), 399 400 .DO (read_queue_data), 401 .DOP (), 402 403 .ECCPARITY (), 404 .SBITERR (), 405 .DBITERR () 406 ); 407 408 409 assign expected_tid = read_queue_data_q[19:12]; 410 assign expected_ftype = read_queue_data_q[11:8]; 411 assign expected_size = read_queue_data_q[7:0]; 412 // }}} End of Response Queue ------------ 413 414 415 // {{{ Response Side Check -------------- 416 417 // collect outgoing requests that require a response, queue them 418 always @(posedge log_clk) begin 419 if (log_rst_q) begin 420 expecting_a_response <= 1'b0; 421 end else if (current_beat_cnt == 0 && ireq_advance_condition) begin 422 expecting_a_response <= (current_ftype == NREAD) || 423 (current_ftype == DOORB) || 424 (current_ftype == MESSG) || 425 ((current_ftype == NWRITE) && (current_ttype == TNWR_R)); 426 end else begin 427 expecting_a_response <= 1'b0; 428 end 429 end 430 always @(posedge log_clk) begin 431 if (log_rst_q) begin 432 write_queue_addr <= 9'h000; 433 end else if (expecting_a_response) begin 434 write_queue_addr <= write_queue_addr + 1; 435 end 436 end 437 438 always @(posedge log_clk) begin 439 if (log_rst_q) begin 440 read_queue_addr <= 9'h000; 441 request_done <= 1'b0; 442 compare_received <= 1'b1; 443 end else if (iresp_advance_condition && val_iresp_tlast && sent_all_packets && 444 (write_queue_addr == read_queue_addr + 1)) begin 445 request_done <= 1'b1; 446 compare_received <= 1'b0; 447 end else if (sent_all_packets && (write_queue_addr == read_queue_addr)) begin 448 request_done <= 1'b1; 449 compare_received <= 1'b0; 450 end else if (iresp_advance_condition && val_iresp_tlast && !request_autocheck_error) begin 451 read_queue_addr <= read_queue_addr + 1; 452 compare_received <= 1'b1; 453 end else if (iresp_advance_condition) begin 454 compare_received <= 1'b0; 455 end 456 end 457 458 always @ (posedge log_clk) begin 459 if (log_rst_q) begin 460 request_autocheck_error <= 1'b0; 461 end else if (compare_received && iresp_advance_condition) begin 462 if(expected_tid != val_iresp_tdata[63:56]) begin 463 // TID mismatch means an error unless it's a message response (MSGs don't use TID) 464 if (!(expected_ftype == MESSG) || !(val_iresp_tdata[51:48] == MSGRSP)) begin 465 request_autocheck_error <= 1'b1; 466 $display ("\t *** TID mismatch Error ***"); 467 end 468 // expecting a Read response 469 end else if (expected_ftype == NREAD && !(val_iresp_tdata[51:48] == TWDATA)) begin 470 request_autocheck_error <= 1'b1; 471 $display ("\t *** NREAD Read Response Not Received ***"); 472 // expecting a Response without data 473 end else if (expected_ftype == NWRITE && !(val_iresp_tdata[51:48] == TNDATA)) begin 474 request_autocheck_error <= 1'b1; 475 $display ("\t *** NWRITE Response Without Data Error ***"); 476 // expecting a Response without data 477 end else if (expected_ftype == DOORB && !(val_iresp_tdata[51:48] == TNDATA)) begin 478 request_autocheck_error <= 1'b1; 479 $display ("\t *** DOORB Response Without Data Error ***"); 480 end 481 end 482 end 483 484 always @ (posedge log_clk) begin 485 if (log_rst_q) begin 486 val_iresp_tready <= 1'b0; 487 delay_assert_tready <= 1'b0; 488 489 end else if (iresp_advance_condition && val_iresp_tlast) begin 490 val_iresp_tready <= 1'b0; 491 delay_assert_tready <= 1'b1; 492 end else if (delay_assert_tready) begin 493 val_iresp_tready <= 1'b0; 494 delay_assert_tready <= 1'b0; 495 end else begin 496 val_iresp_tready <= 1'b1; 497 delay_assert_tready <= 1'b0; 498 end 499 end 500 501 // }}} End Response Side Check ---------- 502 503 504 endmodule 505 // {{{ DISCLAIMER OF LIABILITY 506 // ----------------------------------------------------------------- 507 // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. 508 // 509 // This file contains confidential and proprietary information 510 // of Xilinx, Inc. and is protected under U.S. and 511 // international copyright and other intellectual property 512 // laws. 513 // 514 // DISCLAIMER 515 // This disclaimer is not a license and does not grant any 516 // rights to the materials distributed herewith. Except as 517 // otherwise provided in a valid license issued to you by 518 // Xilinx, and to the maximum extent permitted by applicable 519 // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 520 // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 521 // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 522 // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 523 // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 524 // (2) Xilinx shall not be liable (whether in contract or tort, 525 // including negligence, or under any other theory of 526 // liability) for any loss or damage of any kind or nature 527 // related to, arising under or in connection with these 528 // materials, including for any direct, or any indirect, 529 // special, incidental, or consequential loss or damage 530 // (including loss of data, profits, goodwill, or any type of 531 // loss or damage suffered as a result of any action brought 532 // by a third party) even if such damage or loss was 533 // reasonably foreseeable or Xilinx had been advised of the 534 // possibility of the same. 535 // 536 // CRITICAL APPLICATIONS 537 // Xilinx products are not designed or intended to be fail- 538 // safe, or for use in any application requiring fail-safe 539 // performance, such as life-support or safety devices or 540 // systems, Class III medical devices, nuclear facilities, 541 // applications related to the deployment of airbags, or any 542 // other applications that could lead to death, personal 543 // injury, or severe property or environmental damage 544 // (individually and collectively, "Critical 545 // Applications"). Customer assumes the sole risk and 546 // liability of any use of Xilinx products in Critical 547 // Applications, subject only to applicable laws and 548 // regulations governing limitations on product liability. 549 // 550 // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 551 // PART OF THIS FILE AT ALL TIMES. 552 // }}}
srio_response_gen_srio_gen2_0.v源码
1 // 2 // (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved. 3 // 4 // 5 // This file contains confidential and proprietary information 6 // of Xilinx, Inc. and is protected under U.S. and 7 // international copyright and other intellectual property 8 // laws. 9 // 10 // DISCLAIMER 11 // This disclaimer is not a license and does not grant any 12 // rights to the materials distributed herewith. Except as 13 // otherwise provided in a valid license issued to you by 14 // Xilinx, and to the maximum extent permitted by applicable 15 // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 // (2) Xilinx shall not be liable (whether in contract or tort, 21 // including negligence, or under any other theory of 22 // liability) for any loss or damage of any kind or nature 23 // related to, arising under or in connection with these 24 // materials, including for any direct, or any indirect, 25 // special, incidental, or consequential loss or damage 26 // (including loss of data, profits, goodwill, or any type of 27 // loss or damage suffered as a result of any action brought 28 // by a third party) even if such damage or loss was 29 // reasonably foreseeable or Xilinx had been advised of the 30 // possibility of the same. 31 // 32 // CRITICAL APPLICATIONS 33 // Xilinx products are not designed or intended to be fail- 34 // safe, or for use in any application requiring fail-safe 35 // performance, such as life-support or safety devices or 36 // systems, Class III medical devices, nuclear facilities, 37 // applications related to the deployment of airbags, or any 38 // other applications that could lead to death, personal 39 // injury, or severe property or environmental damage 40 // (individually and collectively, "Critical 41 // Applications"). Customer assumes the sole risk and 42 // liability of any use of Xilinx products in Critical 43 // Applications, subject only to applicable laws and 44 // regulations governing limitations on product liability. 45 // 46 // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 // PART OF THIS FILE AT ALL TIMES. 48 49 `timescale 1ps/1ps 50 51 module srio_response_gen_srio_gen2_0 ( 52 input log_clk, 53 input log_rst, 54 55 input [15:0] deviceid, 56 input [15:0] source_id, 57 input id_override, 58 59 output reg val_tresp_tvalid, 60 input val_tresp_tready, 61 output reg val_tresp_tlast, 62 output reg [63:0] val_tresp_tdata, 63 output [7:0] val_tresp_tkeep, 64 output [31:0] val_tresp_tuser, 65 66 input val_treq_tvalid, 67 output reg val_treq_tready, 68 input val_treq_tlast, 69 input [63:0] val_treq_tdata, 70 input [7:0] val_treq_tkeep, 71 input [31:0] val_treq_tuser 72 ); 73 74 75 // {{{ local parameters ----------------- 76 77 localparam [3:0] NREAD = 4'h2; 78 localparam [3:0] NWRITE = 4'h5; 79 localparam [3:0] SWRITE = 4'h6; 80 localparam [3:0] DOORB = 4'hA; 81 localparam [3:0] MESSG = 4'hB; 82 localparam [3:0] RESP = 4'hD; 83 84 localparam [3:0] TNWR = 4'h4; 85 localparam [3:0] TNWR_R = 4'h5; 86 localparam [3:0] TNRD = 4'h4; 87 88 localparam [3:0] TNDATA = 4'h0; 89 localparam [3:0] MSGRSP = 4'h1; 90 localparam [3:0] TWDATA = 4'h8; 91 92 // }}} End local parameters ------------- 93 94 95 // {{{ wire declarations ---------------- 96 reg [15:0] log_rst_shift; 97 wire log_rst_q = log_rst_shift[15]; 98 99 wire treq_advance_condition = val_treq_tready && val_treq_tvalid; 100 wire tresp_advance_condition = val_tresp_tready && val_tresp_tvalid; 101 102 // request side 103 wire [63:0] response_data_in_d; 104 reg [63:0] response_data_in; 105 reg [8:0] response_wr_address; 106 107 reg generate_a_response; 108 reg first_beat; 109 110 // data storage 111 reg capture_data; 112 reg [8:0] data_store_waddr; 113 reg [8:0] data_store_raddr; 114 wire data_store_wen; 115 wire data_store_ren; 116 wire [63:0] data_store_dout; 117 118 // incoming packet fields 119 wire [7:0] current_tid; 120 wire [3:0] current_ftype; 121 wire [3:0] current_ttype; 122 wire [7:0] current_size; 123 wire [1:0] current_prio; 124 wire [33:0] current_addr; 125 wire [15:0] current_srcid; 126 wire [15:0] dest_id; 127 wire [15:0] src_id; 128 // outgoing packet fields 129 wire [7:0] response_tid; 130 wire [3:0] response_ftype; 131 wire [3:0] response_ttype; 132 wire [7:0] response_size; 133 wire [1:0] response_prio; 134 wire [63:0] response_data_out_d; 135 reg [46:0] response_data_out; // upper 63:47 unused 136 wire [8:0] starting_read_addr; 137 wire pull_from_store; 138 reg pull_from_store_q; 139 reg [8:0] response_rd_address; 140 reg addresses_differ; 141 reg out_of_packet; 142 wire rd_increment; 143 reg rd_increment_q, rd_increment_qq, rd_increment_qqq, rd_increment_qqqq; 144 reg before_first_beat; 145 reg first_packet_transfer; 146 reg first_packet_transfer_q; 147 148 wire [3:0] responding_ttype; 149 wire [63:0] header_beat; 150 wire [4:0] number_of_data_beats; 151 reg [4:0] number_of_data_beats_q; 152 reg [5:0] current_beat_cnt; 153 reg [7:0] data_beat, data_beat_q; 154 155 // }}} End wire declarations ------------ 156 157 158 // {{{ Common-use Signals --------------- 159 160 // Simple Assignments 161 assign val_tresp_tkeep = 8'hFF; 162 assign src_id = id_override ? source_id : deviceid; 163 assign val_tresp_tuser = {src_id, dest_id}; 164 // End Simple Assignments 165 166 always @(posedge log_clk or posedge log_rst) begin 167 if (log_rst) 168 log_rst_shift <= 16'hFFFF; 169 else 170 log_rst_shift <= {log_rst_shift[14:0], 1'b0}; 171 end 172 173 always @(posedge log_clk) begin 174 if (log_rst_q) begin 175 number_of_data_beats_q <= 5'h0; 176 rd_increment_q <= 1'b0; 177 rd_increment_qq <= 1'b0; 178 rd_increment_qqq <= 1'b0; 179 rd_increment_qqqq <= 1'b0; 180 end else begin 181 number_of_data_beats_q <= number_of_data_beats; 182 rd_increment_q <= rd_increment; 183 rd_increment_qq <= rd_increment_q; 184 rd_increment_qqq <= rd_increment_qq; 185 rd_increment_qqqq <= rd_increment_qqq; 186 end 187 end 188 // }}} End Common-use Signals ----------- 189 190 191 // {{{ Request Logic -------------------- 192 193 always @(posedge log_clk) begin 194 if (log_rst_q) begin 195 val_treq_tready <= 1'b0; 196 // buffer full condition 197 end else if (((response_wr_address + 16'h1) == response_rd_address) || 198 ((response_wr_address + 16'h2) == response_rd_address)) begin 199 val_treq_tready <= 1'b0; 200 end else begin 201 val_treq_tready <= 1'b1; 202 end 203 end 204 205 always @(posedge log_clk) begin 206 if (log_rst_q) begin 207 first_beat <= 1'b1; 208 end else if (treq_advance_condition && val_treq_tlast) begin 209 first_beat <= 1'b1; 210 end else if (treq_advance_condition) begin 211 first_beat <= 1'b0; 212 end 213 end 214 assign current_tid = val_treq_tdata[63:56]; 215 assign current_ftype = val_treq_tdata[55:52]; 216 assign current_ttype = val_treq_tdata[51:48]; 217 assign current_size = val_treq_tdata[43:36]; 218 assign current_prio = val_treq_tdata[46:45] + 2'b01; 219 assign current_addr = val_treq_tdata[33:0]; 220 assign current_srcid = val_treq_tuser[31:16]; 221 222 223 // collect incoming requests that require a response, queue them 224 always @(posedge log_clk) begin 225 if (log_rst_q) begin 226 generate_a_response <= 1'b0; 227 end else if (first_beat && treq_advance_condition) begin 228 generate_a_response <= (current_ftype == NREAD) || 229 (current_ftype == DOORB) || 230 (current_ftype == MESSG) || 231 ((current_ftype == NWRITE) && (current_ttype == TNWR_R)); 232 end else begin 233 generate_a_response <= 1'b0; 234 end 235 end 236 // }}} End Request Logic ---------------- 237 238 239 // {{{ Local Data Storage --------------- 240 always @(posedge log_clk) begin 241 if (log_rst_q) begin 242 capture_data <= 1'b0; 243 end else if (first_beat && treq_advance_condition && current_addr[23:16] == 8'h12) begin 244 capture_data <= (current_ftype == SWRITE) || (current_ftype == NWRITE); 245 end else if (treq_advance_condition && val_treq_tlast) begin 246 capture_data <= 1'b0; 247 end 248 end 249 250 assign data_store_wen = capture_data && treq_advance_condition; 251 252 always @(posedge log_clk) begin 253 if (log_rst_q) begin 254 data_store_waddr <= 9'h0; 255 end else if (first_beat && treq_advance_condition) begin 256 data_store_waddr <= {1'b0, current_addr[10:3]}; 257 end else if (treq_advance_condition) begin 258 data_store_waddr <= data_store_waddr + 1; 259 end 260 end 261 262 always @(posedge log_clk) begin 263 if (log_rst_q) begin 264 data_store_raddr <= 9'h0; 265 pull_from_store_q <= 1'b0; 266 end else if (pull_from_store && current_beat_cnt == 0 && !tresp_advance_condition && 267 (rd_increment_qqq || first_packet_transfer)) begin 268 data_store_raddr <= starting_read_addr; 269 pull_from_store_q <= 1'b1; 270 end else if ((pull_from_store_q && tresp_advance_condition) || first_packet_transfer_q || rd_increment_qqqq) begin 271 data_store_raddr <= data_store_raddr + 1; 272 pull_from_store_q <= !(val_tresp_tlast && !rd_increment_qqqq); 273 end 274 end 275 276 assign data_store_ren = val_tresp_tready || !val_tresp_tvalid; 277 278 RAMB36SDP #( 279 .SIM_COLLISION_CHECK("NONE"), 280 .EN_ECC_READ("FALSE"), 281 .EN_ECC_WRITE("FALSE") 282 ) 283 local_data_store ( 284 .DI (val_treq_tdata), 285 .DIP (8'h0), 286 .RDADDR (data_store_raddr), 287 .RDCLK (log_clk), 288 .RDEN (data_store_ren), 289 .REGCE (1'b1), 290 .SSR (log_rst), 291 .WE ({8{data_store_wen}}), 292 .WRADDR (data_store_waddr), 293 .WRCLK (log_clk), 294 .WREN (data_store_wen), 295 296 .DO (data_store_dout), 297 .DOP (), 298 299 .ECCPARITY (), 300 .SBITERR (), 301 .DBITERR () 302 ); 303 // }}} End Local Data Storage ----------- 304 305 306 // {{{ Request Queue -------------------- 307 assign response_data_in_d = {17'h0, current_srcid, current_addr[23:16] == 8'h12, current_addr[10:3], 308 current_prio, current_tid, current_ftype, current_size}; 309 always @ (posedge log_clk) begin 310 response_data_in <= response_data_in_d; 311 end 312 313 always @(posedge log_clk) begin 314 if (log_rst_q) begin 315 out_of_packet <= 1'b0; 316 end else if (rd_increment) begin 317 out_of_packet <= 1'b0; 318 end else if (tresp_advance_condition && val_tresp_tlast) begin 319 out_of_packet <= 1'b1; 320 end 321 end 322 assign rd_increment = ((tresp_advance_condition && val_tresp_tlast) || (out_of_packet)) && 323 (response_rd_address != response_wr_address) && 324 (response_rd_address + 1 != response_wr_address); 325 always @(posedge log_clk) begin 326 if (log_rst_q) begin 327 response_wr_address <= 9'h0; 328 response_rd_address <= 9'h0; 329 end else begin 330 if (generate_a_response) 331 response_wr_address <= response_wr_address + 1; 332 if (rd_increment) 333 response_rd_address <= response_rd_address + 1; 334 end 335 end 336 337 RAMB36SDP #( 338 .SIM_COLLISION_CHECK("NONE"), 339 .EN_ECC_READ("FALSE"), 340 .EN_ECC_WRITE("FALSE") 341 ) 342 response_queue_inst ( 343 .DI (response_data_in), 344 .DIP (8'h0), 345 .RDADDR (response_rd_address), 346 .RDCLK (log_clk), 347 .RDEN (1'b1), 348 .REGCE (1'b1), 349 .SSR (log_rst), 350 .WE ({8{generate_a_response}}), 351 .WRADDR (response_wr_address), 352 .WRCLK (log_clk), 353 .WREN (generate_a_response), 354 355 .DO (response_data_out_d), 356 .DOP (), 357 358 .ECCPARITY (), 359 .SBITERR (), 360 .DBITERR () 361 ); 362 363 always @ (posedge log_clk) begin 364 response_data_out <= response_data_out_d[46:0]; 365 end 366 assign response_tid = response_data_out[19:12]; 367 assign response_ftype = response_data_out[11:8]; 368 assign response_size = response_data_out[7:0]; 369 assign response_prio = response_data_out[21:20]; 370 assign dest_id = response_data_out[46:31]; 371 assign starting_read_addr = {1'b0, response_data_out[29:22]}; 372 assign pull_from_store = response_data_out[30]; 373 374 // }}} End of Request Queue ------------- 375 376 377 // {{{ Response Logic ------------------- 378 assign number_of_data_beats = current_beat_cnt == 0 ? response_size[7:3] : number_of_data_beats_q; 379 380 always @(posedge log_clk) begin 381 if (log_rst_q) begin 382 current_beat_cnt <= 6'h0; 383 end else if (tresp_advance_condition && val_tresp_tlast) begin 384 current_beat_cnt <= 6'h0; 385 end else if (tresp_advance_condition) begin 386 current_beat_cnt <= current_beat_cnt + 1; 387 end 388 end 389 390 always @(posedge log_clk) begin 391 if (log_rst_q) begin 392 val_tresp_tlast <= 1'b0; 393 end else if (responding_ttype == TNDATA || responding_ttype == MSGRSP) begin 394 val_tresp_tlast <= !(tresp_advance_condition && val_tresp_tlast); 395 end else if (current_beat_cnt == {1'b0, number_of_data_beats} && tresp_advance_condition) begin 396 val_tresp_tlast <= !val_tresp_tlast; 397 end else if (val_tresp_tready || !val_tresp_tvalid) begin 398 val_tresp_tlast <= 1'b0; 399 end 400 end 401 402 assign responding_ttype = (response_ftype == NREAD) ? TWDATA : (response_ftype == MESSG) ? MSGRSP : TNDATA; 403 assign header_beat = {response_tid, RESP, responding_ttype, 1'b0, response_prio, 45'h0}; 404 always @(posedge log_clk) begin 405 if (current_beat_cnt == 0 && !tresp_advance_condition) begin 406 val_tresp_tdata <= header_beat; 407 end else if (pull_from_store || pull_from_store_q) begin 408 if (tresp_advance_condition) begin 409 val_tresp_tdata <= data_store_dout; 410 end 411 end else begin 412 val_tresp_tdata <= {8{data_beat}}; 413 end 414 end 415 always @* begin 416 data_beat = data_beat_q; 417 if (tresp_advance_condition && current_beat_cnt != 0) begin 418 data_beat = data_beat_q + 1; 419 end 420 end 421 always @(posedge log_clk) begin 422 if (log_rst_q) begin 423 data_beat_q <= 8'h00; 424 end else begin 425 data_beat_q <= data_beat; 426 end 427 end 428 429 always @(posedge log_clk) begin 430 if (log_rst_q) begin 431 before_first_beat <= 1'b1; 432 end else if (addresses_differ) begin 433 before_first_beat <= 1'b0; 434 end 435 end 436 always @(posedge log_clk) begin 437 if (log_rst_q) begin 438 addresses_differ <= 1'b0; 439 end else if (response_rd_address != response_wr_address) begin 440 addresses_differ <= 1'b1; 441 end 442 end 443 always @(posedge log_clk) begin 444 if (log_rst_q) begin 445 first_packet_transfer <= 1'b0; 446 end else if (before_first_beat && addresses_differ) begin 447 first_packet_transfer <= 1'b1; 448 end else begin 449 first_packet_transfer <= 1'b0; 450 end 451 end 452 always @(posedge log_clk) begin 453 if (log_rst_q) begin 454 first_packet_transfer_q <= 1'b0; 455 end else begin 456 first_packet_transfer_q <= first_packet_transfer; 457 end 458 end 459 always @(posedge log_clk) begin 460 if (log_rst_q) begin 461 val_tresp_tvalid <= 1'b0; 462 end else if (first_packet_transfer_q) begin 463 val_tresp_tvalid <= 1'b1; 464 end else if (rd_increment_qqqq) begin 465 val_tresp_tvalid <= 1'b1; 466 end else if (tresp_advance_condition && val_tresp_tlast) begin 467 val_tresp_tvalid <= 1'b0; 468 end 469 end 470 471 // }}} End Response Logic --------------- 472 473 474 endmodule 475 // {{{ DISCLAIMER OF LIABILITY 476 // ----------------------------------------------------------------- 477 // (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved. 478 // 479 // This file contains confidential and proprietary information 480 // of Xilinx, Inc. and is protected under U.S. and 481 // international copyright and other intellectual property 482 // laws. 483 // 484 // DISCLAIMER 485 // This disclaimer is not a license and does not grant any 486 // rights to the materials distributed herewith. Except as 487 // otherwise provided in a valid license issued to you by 488 // Xilinx, and to the maximum extent permitted by applicable 489 // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 490 // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 491 // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 492 // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 493 // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 494 // (2) Xilinx shall not be liable (whether in contract or tort, 495 // including negligence, or under any other theory of 496 // liability) for any loss or damage of any kind or nature 497 // related to, arising under or in connection with these 498 // materials, including for any direct, or any indirect, 499 // special, incidental, or consequential loss or damage 500 // (including loss of data, profits, goodwill, or any type of 501 // loss or damage suffered as a result of any action brought 502 // by a third party) even if such damage or loss was 503 // reasonably foreseeable or Xilinx had been advised of the 504 // possibility of the same. 505 // 506 // CRITICAL APPLICATIONS 507 // Xilinx products are not designed or intended to be fail- 508 // safe, or for use in any application requiring fail-safe 509 // performance, such as life-support or safety devices or 510 // systems, Class III medical devices, nuclear facilities, 511 // applications related to the deployment of airbags, or any 512 // other applications that could lead to death, personal 513 // injury, or severe property or environmental damage 514 // (individually and collectively, "Critical 515 // Applications"). Customer assumes the sole risk and 516 // liability of any use of Xilinx products in Critical 517 // Applications, subject only to applicable laws and 518 // regulations governing limitations on product liability. 519 // 520 // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 521 // PART OF THIS FILE AT ALL TIMES. 522 // }}}
srio_quick_start_srio_gen2_0.v源码
1 // 2 // (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved. 3 // 4 // 5 // This file contains confidential and proprietary information 6 // of Xilinx, Inc. and is protected under U.S. and 7 // international copyright and other intellectual property 8 // laws. 9 // 10 // DISCLAIMER 11 // This disclaimer is not a license and does not grant any 12 // rights to the materials distributed herewith. Except as 13 // otherwise provided in a valid license issued to you by 14 // Xilinx, and to the maximum extent permitted by applicable 15 // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 // (2) Xilinx shall not be liable (whether in contract or tort, 21 // including negligence, or under any other theory of 22 // liability) for any loss or damage of any kind or nature 23 // related to, arising under or in connection with these 24 // materials, including for any direct, or any indirect, 25 // special, incidental, or consequential loss or damage 26 // (including loss of data, profits, goodwill, or any type of 27 // loss or damage suffered as a result of any action brought 28 // by a third party) even if such damage or loss was 29 // reasonably foreseeable or Xilinx had been advised of the 30 // possibility of the same. 31 // 32 // CRITICAL APPLICATIONS 33 // Xilinx products are not designed or intended to be fail- 34 // safe, or for use in any application requiring fail-safe 35 // performance, such as life-support or safety devices or 36 // systems, Class III medical devices, nuclear facilities, 37 // applications related to the deployment of airbags, or any 38 // other applications that could lead to death, personal 39 // injury, or severe property or environmental damage 40 // (individually and collectively, "Critical 41 // Applications"). Customer assumes the sole risk and 42 // liability of any use of Xilinx products in Critical 43 // Applications, subject only to applicable laws and 44 // regulations governing limitations on product liability. 45 // 46 // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 // PART OF THIS FILE AT ALL TIMES. 48 //---------------------------------------------------------------------- 49 // 50 // SRIO_QUICK_START 51 // Description: 52 // This module sends a fixed set of instructions to the configuration 53 // register space, both local and remote. 54 // 55 // Hierarchy: 56 // SRIO_EXAMPLE_TOP 57 // |____> SRIO_DUT 58 // |____> SRIO_STATISTICS 59 // |____> SRIO_REPORT 60 // |____> SRIO_REQUEST_GEN 61 // |____> SRIO_RESPONSE_GEN 62 // |____> SRIO_QUICK_START 63 // 64 // --------------------------------------------------------------------- 65 66 `timescale 1ps/1ps 67 68 module srio_quick_start_srio_gen2_0 ( 69 input log_clk, 70 input log_rst, 71 72 output reg maintr_awvalid, 73 input maintr_awready, 74 output [31:0] maintr_awaddr, 75 76 output reg maintr_wvalid, 77 input maintr_wready, 78 output [31:0] maintr_wdata, 79 input maintr_bvalid, 80 output maintr_bready, 81 input [1:0] maintr_bresp, 82 83 output reg maintr_arvalid, 84 input maintr_arready, 85 output [31:0] maintr_araddr, 86 87 input maintr_rvalid, 88 output maintr_rready, 89 input [31:0] maintr_rdata, 90 input [1:0] maintr_rresp, 91 92 input go, 93 input [3:0] user_hop, 94 input user_inst, 95 input [23:0] user_addr, 96 input [31:0] user_data, 97 98 input link_initialized, 99 output reg maint_done, 100 output reg maint_autocheck_error 101 ); 102 103 104 // {{{ local parameters ----------------- 105 localparam [8:0] STARTING_ADDRESS = 9'h0; 106 localparam NUMBER_OF_INSTRUCTIONS = 20; 107 108 localparam READ = 1'b1; 109 localparam WRITE = 1'b0; 110 localparam LOCAL = 1'b0; 111 localparam REMTE = 1'b1; 112 113 localparam [3:0] MAINT = 4'h8; 114 115 localparam [3:0] RDREQ = 4'h0; 116 localparam [3:0] WRREQ = 4'h1; 117 118 localparam [7:0] HOP_LOCAL = 8'h00; 119 localparam [7:0] HOP_REMTE = 8'hFF; 120 121 122 `include "maintenance_list.vh" 123 // }}} End local parameters ------------- 124 125 126 // {{{ wire declarations ---------------- 127 reg [15:0] log_rst_shift; 128 wire log_rst_q = log_rst_shift[15]; 129 130 reg [10:0] link_initialized_cnt; 131 wire link_initialized_delay = link_initialized_cnt[10]; 132 133 wire [63:0] maint_data_out_d; 134 reg [61:0] maint_data_out; // upper 63:62 bits unused 135 reg [8:0] maint_address; 136 reg go_q; 137 wire go_rose; 138 139 wire maint_req_advance_condition = (maintr_awready && maintr_awvalid) || 140 (maintr_arready && maintr_arvalid); 141 wire maint_bresp_advance_condition = (maintr_bready && maintr_bvalid); 142 wire maint_resp_advance_condition = (maintr_rready && maintr_rvalid); 143 144 reg last_packet_beat_q, last_packet_beat_qq, last_packet_beat_qqq; 145 reg [15:0] instruction_cnt; 146 wire [32:0] data_mask = { {8{maint_data_out[3]}}, {8{maint_data_out[2]}}, 147 {8{maint_data_out[1]}}, {8{maint_data_out[0]}} }; 148 // }}} End wire declarations ------------ 149 150 151 // {{{ Common-use Signals --------------- 152 153 154 always @(posedge log_clk or posedge log_rst) begin 155 if (log_rst) 156 log_rst_shift <= 16'hFFFF; 157 else 158 log_rst_shift <= {log_rst_shift[14:0], 1'b0}; 159 end 160 161 always @(posedge log_clk) begin 162 if (log_rst_q) begin 163 last_packet_beat_q <= 1'b1; 164 last_packet_beat_qq <= 1'b1; 165 last_packet_beat_qqq <= 1'b1; 166 go_q <= 1'b0; 167 end else begin 168 last_packet_beat_q <= maint_resp_advance_condition || maint_bresp_advance_condition; 169 last_packet_beat_qq <= last_packet_beat_q; 170 last_packet_beat_qqq <= last_packet_beat_qq || !link_initialized_delay; 171 go_q <= go; 172 end 173 end 174 175 // put a sufficient delay on the initialization to improve simulation time. 176 // Not needed for actual hardware but does no damage if kept. 177 always @(posedge log_clk) begin 178 if (log_rst_q) begin 179 link_initialized_cnt <= 0; 180 end else if (link_initialized && !link_initialized_delay) begin 181 link_initialized_cnt <= link_initialized_cnt + 1; 182 end else if (!link_initialized) begin 183 link_initialized_cnt <= 0; 184 end 185 end 186 187 assign go_rose = go && !go_q; 188 // }}} End Common-use Signals ----------- 189 190 191 // {{{ Request Packet Formatter --------- 192 always @(posedge log_clk) begin 193 if (log_rst_q) begin 194 maint_address <= STARTING_ADDRESS; 195 end else if (maint_resp_advance_condition || maint_bresp_advance_condition) begin 196 maint_address <= maint_address + 1; 197 end 198 end 199 200 assign maintr_wdata = go ? user_data : maint_data_out[35:4]; 201 202 assign maintr_bready = 1'b1; 203 assign maintr_rready = 1'b1; 204 205 assign maintr_araddr = go ? { 4'h0, user_hop, user_addr} : maint_data_out[61:37]; 206 assign maintr_awaddr = go ? { 4'h0, user_hop, user_addr} : maint_data_out[61:37]; 207 208 always @(posedge log_clk) begin 209 if (log_rst_q) begin 210 maintr_awvalid <= 1'b0; 211 maintr_wvalid <= 1'b0; 212 maintr_arvalid <= 1'b0; 213 instruction_cnt <= 16'h0; 214 end else if (link_initialized_delay && 215 (instruction_cnt < NUMBER_OF_INSTRUCTIONS && last_packet_beat_qqq) || go_rose) begin 216 maintr_awvalid <= go ? user_inst == WRITE : maint_data_out[36] == WRITE; 217 maintr_wvalid <= go ? user_inst == WRITE : maint_data_out[36] == WRITE; 218 maintr_arvalid <= go ? user_inst == READ : maint_data_out[36] == READ; 219 end else if (maint_req_advance_condition) begin 220 maintr_awvalid <= 1'b0; 221 maintr_wvalid <= 1'b0; 222 maintr_arvalid <= 1'b0; 223 instruction_cnt <= instruction_cnt + 1; 224 end else if (instruction_cnt == NUMBER_OF_INSTRUCTIONS) begin 225 maintr_awvalid <= 1'b0; 226 maintr_wvalid <= 1'b0; 227 maintr_arvalid <= 1'b0; 228 end 229 end 230 // }}} End Request Packet Formatter ----- 231 232 // {{{ Request generation --------------- 233 RAMB36SDP #( 234 .SIM_COLLISION_CHECK("NONE"), 235 .EN_ECC_READ("FALSE"), 236 .EN_ECC_WRITE("FALSE"), 237 238 .INIT_00({MAINTENANCE3 , MAINTENANCE2 , MAINTENANCE1 , MAINTENANCE0} ), 239 .INIT_01({MAINTENANCE7 , MAINTENANCE6 , MAINTENANCE5 , MAINTENANCE4} ), 240 .INIT_02({MAINTENANCE11 , MAINTENANCE10 , MAINTENANCE9 , MAINTENANCE8} ), 241 .INIT_03({MAINTENANCE15 , MAINTENANCE14 , MAINTENANCE13 , MAINTENANCE12} ), 242 .INIT_04({MAINTENANCE19 , MAINTENANCE18 , MAINTENANCE17 , MAINTENANCE16} ), 243 .INIT_05({MAINTENANCE23 , MAINTENANCE22 , MAINTENANCE21 , MAINTENANCE20} ), 244 .INIT_06({MAINTENANCE27 , MAINTENANCE26 , MAINTENANCE25 , MAINTENANCE24} ), 245 .INIT_07({MAINTENANCE31 , MAINTENANCE30 , MAINTENANCE29 , MAINTENANCE28} ), 246 .INIT_08({MAINTENANCE35 , MAINTENANCE34 , MAINTENANCE33 , MAINTENANCE32} ), 247 .INIT_09({MAINTENANCE39 , MAINTENANCE38 , MAINTENANCE37 , MAINTENANCE36} ), 248 .INIT_0A({MAINTENANCE43 , MAINTENANCE42 , MAINTENANCE41 , MAINTENANCE40} ), 249 .INIT_0B({MAINTENANCE47 , MAINTENANCE46 , MAINTENANCE45 , MAINTENANCE44} ), 250 .INIT_0C({MAINTENANCE51 , MAINTENANCE50 , MAINTENANCE49 , MAINTENANCE48} ), 251 .INIT_0D({MAINTENANCE55 , MAINTENANCE54 , MAINTENANCE53 , MAINTENANCE52} ), 252 .INIT_0E({MAINTENANCE59 , MAINTENANCE58 , MAINTENANCE57 , MAINTENANCE56} ), 253 .INIT_0F({MAINTENANCE63 , MAINTENANCE62 , MAINTENANCE61 , MAINTENANCE60} ), 254 .INIT_10({MAINTENANCE67 , MAINTENANCE66 , MAINTENANCE65 , MAINTENANCE64} ), 255 .INIT_11({MAINTENANCE71 , MAINTENANCE70 , MAINTENANCE69 , MAINTENANCE68} ), 256 .INIT_12({MAINTENANCE75 , MAINTENANCE74 , MAINTENANCE73 , MAINTENANCE72} ), 257 .INIT_13({MAINTENANCE79 , MAINTENANCE78 , MAINTENANCE77 , MAINTENANCE76} ), 258 .INIT_14({MAINTENANCE83 , MAINTENANCE82 , MAINTENANCE81 , MAINTENANCE80} ), 259 .INIT_15({MAINTENANCE87 , MAINTENANCE86 , MAINTENANCE85 , MAINTENANCE84} ), 260 .INIT_16({MAINTENANCE91 , MAINTENANCE90 , MAINTENANCE89 , MAINTENANCE88} ), 261 .INIT_17({MAINTENANCE95 , MAINTENANCE94 , MAINTENANCE93 , MAINTENANCE92} ), 262 .INIT_18({MAINTENANCE99 , MAINTENANCE98 , MAINTENANCE97 , MAINTENANCE96} ), 263 .INIT_19({MAINTENANCE103, MAINTENANCE102, MAINTENANCE101, MAINTENANCE100}), 264 .INIT_1A({MAINTENANCE107, MAINTENANCE106, MAINTENANCE105, MAINTENANCE104}), 265 .INIT_1B({MAINTENANCE111, MAINTENANCE110, MAINTENANCE109, MAINTENANCE108}), 266 .INIT_1C({MAINTENANCE115, MAINTENANCE114, MAINTENANCE113, MAINTENANCE112}), 267 .INIT_1D({MAINTENANCE119, MAINTENANCE118, MAINTENANCE117, MAINTENANCE116}), 268 .INIT_1E({MAINTENANCE123, MAINTENANCE122, MAINTENANCE121, MAINTENANCE120}), 269 .INIT_1F({MAINTENANCE127, MAINTENANCE126, MAINTENANCE125, MAINTENANCE124}), 270 .INIT_20({MAINTENANCE131, MAINTENANCE130, MAINTENANCE129, MAINTENANCE128}), 271 .INIT_21({MAINTENANCE135, MAINTENANCE134, MAINTENANCE133, MAINTENANCE132}), 272 .INIT_22({MAINTENANCE139, MAINTENANCE138, MAINTENANCE137, MAINTENANCE136}), 273 .INIT_23({MAINTENANCE143, MAINTENANCE142, MAINTENANCE141, MAINTENANCE140}), 274 .INIT_24({MAINTENANCE147, MAINTENANCE146, MAINTENANCE145, MAINTENANCE144}), 275 .INIT_25({MAINTENANCE151, MAINTENANCE150, MAINTENANCE149, MAINTENANCE148}), 276 .INIT_26({MAINTENANCE155, MAINTENANCE154, MAINTENANCE153, MAINTENANCE152}), 277 .INIT_27({MAINTENANCE159, MAINTENANCE158, MAINTENANCE157, MAINTENANCE156}), 278 .INIT_28({MAINTENANCE163, MAINTENANCE162, MAINTENANCE161, MAINTENANCE160}), 279 .INIT_29({MAINTENANCE167, MAINTENANCE166, MAINTENANCE165, MAINTENANCE164}), 280 .INIT_2A({MAINTENANCE171, MAINTENANCE170, MAINTENANCE169, MAINTENANCE168}), 281 .INIT_2B({MAINTENANCE175, MAINTENANCE174, MAINTENANCE173, MAINTENANCE172}), 282 .INIT_2C({MAINTENANCE179, MAINTENANCE178, MAINTENANCE177, MAINTENANCE176}), 283 .INIT_2D({MAINTENANCE183, MAINTENANCE182, MAINTENANCE181, MAINTENANCE180}), 284 .INIT_2E({MAINTENANCE187, MAINTENANCE186, MAINTENANCE185, MAINTENANCE184}), 285 .INIT_2F({MAINTENANCE191, MAINTENANCE190, MAINTENANCE189, MAINTENANCE188}), 286 .INIT_30({MAINTENANCE195, MAINTENANCE194, MAINTENANCE193, MAINTENANCE192}), 287 .INIT_31({MAINTENANCE199, MAINTENANCE198, MAINTENANCE197, MAINTENANCE196}), 288 .INIT_32({MAINTENANCE203, MAINTENANCE202, MAINTENANCE201, MAINTENANCE200}), 289 .INIT_33({MAINTENANCE207, MAINTENANCE206, MAINTENANCE205, MAINTENANCE204}), 290 .INIT_34({MAINTENANCE211, MAINTENANCE210, MAINTENANCE209, MAINTENANCE208}), 291 .INIT_35({MAINTENANCE215, MAINTENANCE214, MAINTENANCE213, MAINTENANCE212}), 292 .INIT_36({MAINTENANCE219, MAINTENANCE218, MAINTENANCE217, MAINTENANCE216}), 293 .INIT_37({MAINTENANCE223, MAINTENANCE222, MAINTENANCE221, MAINTENANCE220}), 294 .INIT_38({MAINTENANCE227, MAINTENANCE226, MAINTENANCE225, MAINTENANCE224}), 295 .INIT_39({MAINTENANCE231, MAINTENANCE230, MAINTENANCE229, MAINTENANCE228}), 296 .INIT_3A({MAINTENANCE235, MAINTENANCE234, MAINTENANCE233, MAINTENANCE232}), 297 .INIT_3B({MAINTENANCE239, MAINTENANCE238, MAINTENANCE237, MAINTENANCE236}), 298 .INIT_3C({MAINTENANCE243, MAINTENANCE242, MAINTENANCE241, MAINTENANCE240}), 299 .INIT_3D({MAINTENANCE247, MAINTENANCE246, MAINTENANCE245, MAINTENANCE244}), 300 .INIT_3E({MAINTENANCE251, MAINTENANCE250, MAINTENANCE249, MAINTENANCE248}), 301 .INIT_3F({MAINTENANCE255, MAINTENANCE254, MAINTENANCE253, MAINTENANCE252}), 302 .INIT_40({MAINTENANCE259, MAINTENANCE258, MAINTENANCE257, MAINTENANCE256}), 303 .INIT_41({MAINTENANCE263, MAINTENANCE262, MAINTENANCE261, MAINTENANCE260}), 304 .INIT_42({MAINTENANCE267, MAINTENANCE266, MAINTENANCE265, MAINTENANCE264}), 305 .INIT_43({MAINTENANCE271, MAINTENANCE270, MAINTENANCE269, MAINTENANCE268}), 306 .INIT_44({MAINTENANCE275, MAINTENANCE274, MAINTENANCE273, MAINTENANCE272}), 307 .INIT_45({MAINTENANCE279, MAINTENANCE278, MAINTENANCE277, MAINTENANCE276}), 308 .INIT_46({MAINTENANCE283, MAINTENANCE282, MAINTENANCE281, MAINTENANCE280}), 309 .INIT_47({MAINTENANCE287, MAINTENANCE286, MAINTENANCE285, MAINTENANCE284}), 310 .INIT_48({MAINTENANCE291, MAINTENANCE290, MAINTENANCE289, MAINTENANCE288}), 311 .INIT_49({MAINTENANCE295, MAINTENANCE294, MAINTENANCE293, MAINTENANCE292}), 312 .INIT_4A({MAINTENANCE299, MAINTENANCE298, MAINTENANCE297, MAINTENANCE296}), 313 .INIT_4B({MAINTENANCE303, MAINTENANCE302, MAINTENANCE301, MAINTENANCE300}), 314 .INIT_4C({MAINTENANCE307, MAINTENANCE306, MAINTENANCE305, MAINTENANCE304}), 315 .INIT_4D({MAINTENANCE311, MAINTENANCE310, MAINTENANCE309, MAINTENANCE308}), 316 .INIT_4E({MAINTENANCE315, MAINTENANCE314, MAINTENANCE313, MAINTENANCE312}), 317 .INIT_4F({MAINTENANCE319, MAINTENANCE318, MAINTENANCE317, MAINTENANCE316}), 318 .INIT_50({MAINTENANCE323, MAINTENANCE322, MAINTENANCE321, MAINTENANCE320}), 319 .INIT_51({MAINTENANCE327, MAINTENANCE326, MAINTENANCE325, MAINTENANCE324}), 320 .INIT_52({MAINTENANCE331, MAINTENANCE330, MAINTENANCE329, MAINTENANCE328}), 321 .INIT_53({MAINTENANCE335, MAINTENANCE334, MAINTENANCE333, MAINTENANCE332}), 322 .INIT_54({MAINTENANCE339, MAINTENANCE338, MAINTENANCE337, MAINTENANCE336}), 323 .INIT_55({MAINTENANCE343, MAINTENANCE342, MAINTENANCE341, MAINTENANCE340}), 324 .INIT_56({MAINTENANCE347, MAINTENANCE346, MAINTENANCE345, MAINTENANCE344}), 325 .INIT_57({MAINTENANCE351, MAINTENANCE350, MAINTENANCE349, MAINTENANCE348}), 326 .INIT_58({MAINTENANCE355, MAINTENANCE354, MAINTENANCE353, MAINTENANCE352}), 327 .INIT_59({MAINTENANCE359, MAINTENANCE358, MAINTENANCE357, MAINTENANCE356}), 328 .INIT_5A({MAINTENANCE363, MAINTENANCE362, MAINTENANCE361, MAINTENANCE360}), 329 .INIT_5B({MAINTENANCE367, MAINTENANCE366, MAINTENANCE365, MAINTENANCE364}), 330 .INIT_5C({MAINTENANCE371, MAINTENANCE370, MAINTENANCE369, MAINTENANCE368}), 331 .INIT_5D({MAINTENANCE375, MAINTENANCE374, MAINTENANCE373, MAINTENANCE372}), 332 .INIT_5E({MAINTENANCE379, MAINTENANCE378, MAINTENANCE377, MAINTENANCE376}), 333 .INIT_5F({MAINTENANCE383, MAINTENANCE382, MAINTENANCE381, MAINTENANCE380}), 334 .INIT_60({MAINTENANCE387, MAINTENANCE386, MAINTENANCE385, MAINTENANCE384}), 335 .INIT_61({MAINTENANCE391, MAINTENANCE390, MAINTENANCE389, MAINTENANCE388}), 336 .INIT_62({MAINTENANCE395, MAINTENANCE394, MAINTENANCE393, MAINTENANCE392}), 337 .INIT_63({MAINTENANCE399, MAINTENANCE398, MAINTENANCE397, MAINTENANCE396}), 338 .INIT_64({MAINTENANCE403, MAINTENANCE402, MAINTENANCE401, MAINTENANCE400}), 339 .INIT_65({MAINTENANCE407, MAINTENANCE406, MAINTENANCE405, MAINTENANCE404}), 340 .INIT_66({MAINTENANCE411, MAINTENANCE410, MAINTENANCE409, MAINTENANCE408}), 341 .INIT_67({MAINTENANCE415, MAINTENANCE414, MAINTENANCE413, MAINTENANCE412}), 342 .INIT_68({MAINTENANCE419, MAINTENANCE418, MAINTENANCE417, MAINTENANCE416}), 343 .INIT_69({MAINTENANCE423, MAINTENANCE422, MAINTENANCE421, MAINTENANCE420}), 344 .INIT_6A({MAINTENANCE427, MAINTENANCE426, MAINTENANCE425, MAINTENANCE424}), 345 .INIT_6B({MAINTENANCE431, MAINTENANCE430, MAINTENANCE429, MAINTENANCE428}), 346 .INIT_6C({MAINTENANCE435, MAINTENANCE434, MAINTENANCE433, MAINTENANCE432}), 347 .INIT_6D({MAINTENANCE439, MAINTENANCE438, MAINTENANCE437, MAINTENANCE436}), 348 .INIT_6E({MAINTENANCE443, MAINTENANCE442, MAINTENANCE441, MAINTENANCE440}), 349 .INIT_6F({MAINTENANCE447, MAINTENANCE446, MAINTENANCE445, MAINTENANCE444}), 350 .INIT_70({MAINTENANCE451, MAINTENANCE450, MAINTENANCE449, MAINTENANCE448}), 351 .INIT_71({MAINTENANCE455, MAINTENANCE454, MAINTENANCE453, MAINTENANCE452}), 352 .INIT_72({MAINTENANCE459, MAINTENANCE458, MAINTENANCE457, MAINTENANCE456}), 353 .INIT_73({MAINTENANCE463, MAINTENANCE462, MAINTENANCE461, MAINTENANCE460}), 354 .INIT_74({MAINTENANCE467, MAINTENANCE466, MAINTENANCE465, MAINTENANCE464}), 355 .INIT_75({MAINTENANCE471, MAINTENANCE470, MAINTENANCE469, MAINTENANCE468}), 356 .INIT_76({MAINTENANCE475, MAINTENANCE474, MAINTENANCE473, MAINTENANCE472}), 357 .INIT_77({MAINTENANCE479, MAINTENANCE478, MAINTENANCE477, MAINTENANCE476}), 358 .INIT_78({MAINTENANCE483, MAINTENANCE482, MAINTENANCE481, MAINTENANCE480}), 359 .INIT_79({MAINTENANCE487, MAINTENANCE486, MAINTENANCE485, MAINTENANCE484}), 360 .INIT_7A({MAINTENANCE491, MAINTENANCE490, MAINTENANCE489, MAINTENANCE488}), 361 .INIT_7B({MAINTENANCE495, MAINTENANCE494, MAINTENANCE493, MAINTENANCE492}), 362 .INIT_7C({MAINTENANCE499, MAINTENANCE498, MAINTENANCE497, MAINTENANCE496}), 363 .INIT_7D({MAINTENANCE503, MAINTENANCE502, MAINTENANCE501, MAINTENANCE500}), 364 .INIT_7E({MAINTENANCE507, MAINTENANCE506, MAINTENANCE505, MAINTENANCE504}), 365 .INIT_7F({MAINTENANCE511, MAINTENANCE510, MAINTENANCE509, MAINTENANCE508}) 366 ) 367 maintenance_data_inst ( 368 .DI (64'h0), 369 .DIP (8'h0), 370 .RDADDR (maint_address), 371 .RDCLK (log_clk), 372 .RDEN (1'b1), 373 .REGCE (1'b1), 374 .SSR (log_rst), 375 .WE (8'h0), 376 .WRADDR (9'h0), 377 .WRCLK (log_clk), 378 .WREN (1'b0), 379 380 .DO (maint_data_out_d), 381 .DOP (), 382 383 .ECCPARITY (), 384 .SBITERR (), 385 .DBITERR () 386 ); 387 always @ (posedge log_clk) begin 388 maint_data_out <= maint_data_out_d[61:0]; 389 end 390 391 392 // }}} End of Request Generation -------- 393 394 395 // {{{ Response Side Check -------------- 396 397 always @ (posedge log_clk) begin 398 if (log_rst_q) begin 399 maint_autocheck_error <= 1'b0; 400 end else if (maint_resp_advance_condition && maint_data_out[36] == READ) begin 401 if ((maintr_wdata & data_mask) != (maintr_rdata & data_mask)) begin 402 maint_autocheck_error <= 1'b1; 403 end else begin 404 maint_autocheck_error <= 1'b0; 405 end 406 end 407 end 408 409 always @ (posedge log_clk) begin 410 if (log_rst_q) begin 411 maint_done <= 1'b0; 412 end else if ((instruction_cnt == NUMBER_OF_INSTRUCTIONS) && 413 (maint_bresp_advance_condition || maint_resp_advance_condition)) begin 414 maint_done <= 1'b1; 415 end 416 end 417 418 // }}} End Response Side Check ---------- 419 420 421 endmodule 422 // {{{ DISCLAIMER OF LIABILITY 423 // ----------------------------------------------------------------- 424 // (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved. 425 // 426 // This file contains confidential and proprietary information 427 // of Xilinx, Inc. and is protected under U.S. and 428 // international copyright and other intellectual property 429 // laws. 430 // 431 // DISCLAIMER 432 // This disclaimer is not a license and does not grant any 433 // rights to the materials distributed herewith. Except as 434 // otherwise provided in a valid license issued to you by 435 // Xilinx, and to the maximum extent permitted by applicable 436 // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 437 // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 438 // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 439 // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 440 // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 441 // (2) Xilinx shall not be liable (whether in contract or tort, 442 // including negligence, or under any other theory of 443 // liability) for any loss or damage of any kind or nature 444 // related to, arising under or in connection with these 445 // materials, including for any direct, or any indirect, 446 // special, incidental, or consequential loss or damage 447 // (including loss of data, profits, goodwill, or any type of 448 // loss or damage suffered as a result of any action brought 449 // by a third party) even if such damage or loss was 450 // reasonably foreseeable or Xilinx had been advised of the 451 // possibility of the same. 452 // 453 // CRITICAL APPLICATIONS 454 // Xilinx products are not designed or intended to be fail- 455 // safe, or for use in any application requiring fail-safe 456 // performance, such as life-support or safety devices or 457 // systems, Class III medical devices, nuclear facilities, 458 // applications related to the deployment of airbags, or any 459 // other applications that could lead to death, personal 460 // injury, or severe property or environmental damage 461 // (individually and collectively, "Critical 462 // Applications"). Customer assumes the sole risk and 463 // liability of any use of Xilinx products in Critical 464 // Applications, subject only to applicable laws and 465 // regulations governing limitations on product liability. 466 // 467 // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 468 // PART OF THIS FILE AT ALL TIMES. 469 // }}}
maintenance_list.vh源码
1 //----------------------------------------------------------------------------- 2 // 3 // (c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. 4 // 5 // 6 // This file contains confidential and proprietary information 7 // of Xilinx, Inc. and is protected under U.S. and 8 // international copyright and other intellectual property 9 // laws. 10 // 11 // DISCLAIMER 12 // This disclaimer is not a license and does not grant any 13 // rights to the materials distributed herewith. Except as 14 // otherwise provided in a valid license issued to you by 15 // Xilinx, and to the maximum extent permitted by applicable 16 // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 // (2) Xilinx shall not be liable (whether in contract or tort, 22 // including negligence, or under any other theory of 23 // liability) for any loss or damage of any kind or nature 24 // related to, arising under or in connection with these 25 // materials, including for any direct, or any indirect, 26 // special, incidental, or consequential loss or damage 27 // (including loss of data, profits, goodwill, or any type of 28 // loss or damage suffered as a result of any action brought 29 // by a third party) even if such damage or loss was 30 // reasonably foreseeable or Xilinx had been advised of the 31 // possibility of the same. 32 // 33 // CRITICAL APPLICATIONS 34 // Xilinx products are not designed or intended to be fail- 35 // safe, or for use in any application requiring fail-safe 36 // performance, such as life-support or safety devices or 37 // systems, Class III medical devices, nuclear facilities, 38 // applications related to the deployment of airbags, or any 39 // other applications that could lead to death, personal 40 // injury, or severe property or environmental damage 41 // (individually and collectively, "Critical 42 // Applications"). Customer assumes the sole risk and 43 // liability of any use of Xilinx products in Critical 44 // Applications, subject only to applicable laws and 45 // regulations governing limitations on product liability. 46 // 47 // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 // PART OF THIS FILE AT ALL TIMES. 49 //----------------------------------------------------------------------------- 50 51 // RSVD, LOCAL/REMTE, ADDRESS, RD/WR, DATA, DATA MASK 52 localparam [63:0] MAINTENANCE0 = {2'b0, REMTE, 24'h000000, READ, 32'h0480000E, 4'hF}; 53 localparam [63:0] MAINTENANCE1 = {2'b0, LOCAL, 24'h000000, READ, 32'h0480000E, 4'hF}; 54 localparam [63:0] MAINTENANCE2 = {2'b0, REMTE, 24'h000060, WRITE, 32'hDEADBEEF, 4'h0}; 55 localparam [63:0] MAINTENANCE3 = {2'b0, REMTE, 24'h000060, READ, 32'h00ADBEEF, 4'hF}; 56 57 localparam [63:0] MAINTENANCE4 = {2'b0, LOCAL, 24'h00005C, WRITE, 32'hFFFFFFFF, 4'h0}; 58 localparam [63:0] MAINTENANCE5 = {2'b0, LOCAL, 24'h00005C, READ, 32'h7FE00000, 4'hF}; 59 localparam [63:0] MAINTENANCE6 = {2'b0, REMTE, 24'h00005C, WRITE, 32'hFFFFFFFF, 4'h0}; 60 localparam [63:0] MAINTENANCE7 = {2'b0, REMTE, 24'h00005C, READ, 32'h7FE00000, 4'hF}; 61 62 localparam [63:0] MAINTENANCE8 = {2'b0, REMTE, 24'h010000, WRITE, 32'hFF020304, 4'h0}; 63 localparam [63:0] MAINTENANCE9 = {2'b0, LOCAL, 24'h010000, READ, 32'h00020304, 4'h0}; 64 localparam [63:0] MAINTENANCE10 = {2'b0, LOCAL, 24'h010000, WRITE, 32'h00030405, 4'h0}; 65 localparam [63:0] MAINTENANCE11 = {2'b0, REMTE, 24'h010000, READ, 32'h00030405, 4'h0}; 66 67 localparam [63:0] MAINTENANCE12 = {2'b0, REMTE, 24'h000120, WRITE, 32'hFFFFFFFF, 4'h0}; 68 localparam [63:0] MAINTENANCE13 = {2'b0, REMTE, 24'h000120, READ, 32'hFFFFFF00, 4'h0}; 69 localparam [63:0] MAINTENANCE14 = {2'b0, LOCAL, 24'h000124, WRITE, 32'h01020304, 4'h0}; 70 localparam [63:0] MAINTENANCE15 = {2'b0, LOCAL, 24'h000124, READ, 32'h01020300, 4'h0}; 71 72 localparam [63:0] MAINTENANCE16 = {2'b0, LOCAL, 24'h000410, READ, 32'h00007FC8, 4'h0}; 73 localparam [63:0] MAINTENANCE17 = {2'b0, LOCAL, 24'h000430, READ, 32'h00107FC8, 4'h0}; 74 localparam [63:0] MAINTENANCE18 = {2'b0, REMTE, 24'h000450, READ, 32'h00207FC8, 4'h0}; 75 localparam [63:0] MAINTENANCE19 = {2'b0, REMTE, 24'h000470, READ, 32'h00307FC8, 4'h0}; 76 77 localparam [63:0] MAINTENANCE20 = {64'h0000000000000000}; 78 localparam [63:0] MAINTENANCE21 = {64'h0000000000000000}; 79 80 localparam [63:0] MAINTENANCE22 = {64'h0000000000000000}; 81 localparam [63:0] MAINTENANCE23 = {64'h0000000000000000}; 82 localparam [63:0] MAINTENANCE24 = {64'h0000000000000000}; 83 localparam [63:0] MAINTENANCE25 = {64'h0000000000000000}; 84 localparam [63:0] MAINTENANCE26 = {64'h0000000000000000}; 85 localparam [63:0] MAINTENANCE27 = {64'h0000000000000000}; 86 localparam [63:0] MAINTENANCE28 = {64'h0000000000000000}; 87 localparam [63:0] MAINTENANCE29 = {64'h0000000000000000}; 88 localparam [63:0] MAINTENANCE30 = {64'h0000000000000000}; 89 localparam [63:0] MAINTENANCE31 = {64'h0000000000000000}; 90 localparam [63:0] MAINTENANCE32 = {64'h0000000000000000}; 91 localparam [63:0] MAINTENANCE33 = {64'h0000000000000000}; 92 localparam [63:0] MAINTENANCE34 = {64'h0000000000000000}; 93 localparam [63:0] MAINTENANCE35 = {64'h0000000000000000}; 94 localparam [63:0] MAINTENANCE36 = {64'h0000000000000000}; 95 localparam [63:0] MAINTENANCE37 = {64'h0000000000000000}; 96 localparam [63:0] MAINTENANCE38 = {64'h0000000000000000}; 97 localparam [63:0] MAINTENANCE39 = {64'h0000000000000000}; 98 localparam [63:0] MAINTENANCE40 = {64'h0000000000000000}; 99 localparam [63:0] MAINTENANCE41 = {64'h0000000000000000}; 100 localparam [63:0] MAINTENANCE42 = {64'h0000000000000000}; 101 localparam [63:0] MAINTENANCE43 = {64'h0000000000000000}; 102 localparam [63:0] MAINTENANCE44 = {64'h0000000000000000}; 103 localparam [63:0] MAINTENANCE45 = {64'h0000000000000000}; 104 localparam [63:0] MAINTENANCE46 = {64'h0000000000000000}; 105 localparam [63:0] MAINTENANCE47 = {64'h0000000000000000}; 106 localparam [63:0] MAINTENANCE48 = {64'h0000000000000000}; 107 localparam [63:0] MAINTENANCE49 = {64'h0000000000000000}; 108 localparam [63:0] MAINTENANCE50 = {64'h0000000000000000}; 109 localparam [63:0] MAINTENANCE51 = {64'h0000000000000000}; 110 localparam [63:0] MAINTENANCE52 = {64'h0000000000000000}; 111 localparam [63:0] MAINTENANCE53 = {64'h0000000000000000}; 112 localparam [63:0] MAINTENANCE54 = {64'h0000000000000000}; 113 localparam [63:0] MAINTENANCE55 = {64'h0000000000000000}; 114 localparam [63:0] MAINTENANCE56 = {64'h0000000000000000}; 115 localparam [63:0] MAINTENANCE57 = {64'h0000000000000000}; 116 localparam [63:0] MAINTENANCE58 = {64'h0000000000000000}; 117 localparam [63:0] MAINTENANCE59 = {64'h0000000000000000}; 118 localparam [63:0] MAINTENANCE60 = {64'h0000000000000000}; 119 localparam [63:0] MAINTENANCE61 = {64'h0000000000000000}; 120 localparam [63:0] MAINTENANCE62 = {64'h0000000000000000}; 121 localparam [63:0] MAINTENANCE63 = {64'h0000000000000000}; 122 localparam [63:0] MAINTENANCE64 = {64'h0000000000000000}; 123 localparam [63:0] MAINTENANCE65 = {64'h0000000000000000}; 124 localparam [63:0] MAINTENANCE66 = {64'h0000000000000000}; 125 localparam [63:0] MAINTENANCE67 = {64'h0000000000000000}; 126 localparam [63:0] MAINTENANCE68 = {64'h0000000000000000}; 127 localparam [63:0] MAINTENANCE69 = {64'h0000000000000000}; 128 localparam [63:0] MAINTENANCE70 = {64'h0000000000000000}; 129 localparam [63:0] MAINTENANCE71 = {64'h0000000000000000}; 130 localparam [63:0] MAINTENANCE72 = {64'h0000000000000000}; 131 localparam [63:0] MAINTENANCE73 = {64'h0000000000000000}; 132 localparam [63:0] MAINTENANCE74 = {64'h0000000000000000}; 133 localparam [63:0] MAINTENANCE75 = {64'h0000000000000000}; 134 localparam [63:0] MAINTENANCE76 = {64'h0000000000000000}; 135 localparam [63:0] MAINTENANCE77 = {64'h0000000000000000}; 136 localparam [63:0] MAINTENANCE78 = {64'h0000000000000000}; 137 localparam [63:0] MAINTENANCE79 = {64'h0000000000000000}; 138 localparam [63:0] MAINTENANCE80 = {64'h0000000000000000}; 139 localparam [63:0] MAINTENANCE81 = {64'h0000000000000000}; 140 localparam [63:0] MAINTENANCE82 = {64'h0000000000000000}; 141 localparam [63:0] MAINTENANCE83 = {64'h0000000000000000}; 142 localparam [63:0] MAINTENANCE84 = {64'h0000000000000000}; 143 localparam [63:0] MAINTENANCE85 = {64'h0000000000000000}; 144 localparam [63:0] MAINTENANCE86 = {64'h0000000000000000}; 145 localparam [63:0] MAINTENANCE87 = {64'h0000000000000000}; 146 localparam [63:0] MAINTENANCE88 = {64'h0000000000000000}; 147 localparam [63:0] MAINTENANCE89 = {64'h0000000000000000}; 148 localparam [63:0] MAINTENANCE90 = {64'h0000000000000000}; 149 localparam [63:0] MAINTENANCE91 = {64'h0000000000000000}; 150 localparam [63:0] MAINTENANCE92 = {64'h0000000000000000}; 151 localparam [63:0] MAINTENANCE93 = {64'h0000000000000000}; 152 localparam [63:0] MAINTENANCE94 = {64'h0000000000000000}; 153 localparam [63:0] MAINTENANCE95 = {64'h0000000000000000}; 154 localparam [63:0] MAINTENANCE96 = {64'h0000000000000000}; 155 localparam [63:0] MAINTENANCE97 = {64'h0000000000000000}; 156 localparam [63:0] MAINTENANCE98 = {64'h0000000000000000}; 157 localparam [63:0] MAINTENANCE99 = {64'h0000000000000000}; 158 localparam [63:0] MAINTENANCE100 = {64'h0000000000000000}; 159 localparam [63:0] MAINTENANCE101 = {64'h0000000000000000}; 160 localparam [63:0] MAINTENANCE102 = {64'h0000000000000000}; 161 localparam [63:0] MAINTENANCE103 = {64'h0000000000000000}; 162 localparam [63:0] MAINTENANCE104 = {64'h0000000000000000}; 163 localparam [63:0] MAINTENANCE105 = {64'h0000000000000000}; 164 localparam [63:0] MAINTENANCE106 = {64'h0000000000000000}; 165 localparam [63:0] MAINTENANCE107 = {64'h0000000000000000}; 166 localparam [63:0] MAINTENANCE108 = {64'h0000000000000000}; 167 localparam [63:0] MAINTENANCE109 = {64'h0000000000000000}; 168 localparam [63:0] MAINTENANCE110 = {64'h0000000000000000}; 169 localparam [63:0] MAINTENANCE111 = {64'h0000000000000000}; 170 localparam [63:0] MAINTENANCE112 = {64'h0000000000000000}; 171 localparam [63:0] MAINTENANCE113 = {64'h0000000000000000}; 172 localparam [63:0] MAINTENANCE114 = {64'h0000000000000000}; 173 localparam [63:0] MAINTENANCE115 = {64'h0000000000000000}; 174 localparam [63:0] MAINTENANCE116 = {64'h0000000000000000}; 175 localparam [63:0] MAINTENANCE117 = {64'h0000000000000000}; 176 localparam [63:0] MAINTENANCE118 = {64'h0000000000000000}; 177 localparam [63:0] MAINTENANCE119 = {64'h0000000000000000}; 178 localparam [63:0] MAINTENANCE120 = {64'h0000000000000000}; 179 localparam [63:0] MAINTENANCE121 = {64'h0000000000000000}; 180 localparam [63:0] MAINTENANCE122 = {64'h0000000000000000}; 181 localparam [63:0] MAINTENANCE123 = {64'h0000000000000000}; 182 localparam [63:0] MAINTENANCE124 = {64'h0000000000000000}; 183 localparam [63:0] MAINTENANCE125 = {64'h0000000000000000}; 184 localparam [63:0] MAINTENANCE126 = {64'h0000000000000000}; 185 localparam [63:0] MAINTENANCE127 = {64'h0000000000000000}; 186 localparam [63:0] MAINTENANCE128 = {64'h0000000000000000}; 187 localparam [63:0] MAINTENANCE129 = {64'h0000000000000000}; 188 localparam [63:0] MAINTENANCE130 = {64'h0000000000000000}; 189 localparam [63:0] MAINTENANCE131 = {64'h0000000000000000}; 190 localparam [63:0] MAINTENANCE132 = {64'h0000000000000000}; 191 localparam [63:0] MAINTENANCE133 = {64'h0000000000000000}; 192 localparam [63:0] MAINTENANCE134 = {64'h0000000000000000}; 193 localparam [63:0] MAINTENANCE135 = {64'h0000000000000000}; 194 localparam [63:0] MAINTENANCE136 = {64'h0000000000000000}; 195 localparam [63:0] MAINTENANCE137 = {64'h0000000000000000}; 196 localparam [63:0] MAINTENANCE138 = {64'h0000000000000000}; 197 localparam [63:0] MAINTENANCE139 = {64'h0000000000000000}; 198 localparam [63:0] MAINTENANCE140 = {64'h0000000000000000}; 199 localparam [63:0] MAINTENANCE141 = {64'h0000000000000000}; 200 localparam [63:0] MAINTENANCE142 = {64'h0000000000000000}; 201 localparam [63:0] MAINTENANCE143 = {64'h0000000000000000}; 202 localparam [63:0] MAINTENANCE144 = {64'h0000000000000000}; 203 localparam [63:0] MAINTENANCE145 = {64'h0000000000000000}; 204 localparam [63:0] MAINTENANCE146 = {64'h0000000000000000}; 205 localparam [63:0] MAINTENANCE147 = {64'h0000000000000000}; 206 localparam [63:0] MAINTENANCE148 = {64'h0000000000000000}; 207 localparam [63:0] MAINTENANCE149 = {64'h0000000000000000}; 208 localparam [63:0] MAINTENANCE150 = {64'h0000000000000000}; 209 localparam [63:0] MAINTENANCE151 = {64'h0000000000000000}; 210 localparam [63:0] MAINTENANCE152 = {64'h0000000000000000}; 211 localparam [63:0] MAINTENANCE153 = {64'h0000000000000000}; 212 localparam [63:0] MAINTENANCE154 = {64'h0000000000000000}; 213 localparam [63:0] MAINTENANCE155 = {64'h0000000000000000}; 214 localparam [63:0] MAINTENANCE156 = {64'h0000000000000000}; 215 localparam [63:0] MAINTENANCE157 = {64'h0000000000000000}; 216 localparam [63:0] MAINTENANCE158 = {64'h0000000000000000}; 217 localparam [63:0] MAINTENANCE159 = {64'h0000000000000000}; 218 localparam [63:0] MAINTENANCE160 = {64'h0000000000000000}; 219 localparam [63:0] MAINTENANCE161 = {64'h0000000000000000}; 220 localparam [63:0] MAINTENANCE162 = {64'h0000000000000000}; 221 localparam [63:0] MAINTENANCE163 = {64'h0000000000000000}; 222 localparam [63:0] MAINTENANCE164 = {64'h0000000000000000}; 223 localparam [63:0] MAINTENANCE165 = {64'h0000000000000000}; 224 localparam [63:0] MAINTENANCE166 = {64'h0000000000000000}; 225 localparam [63:0] MAINTENANCE167 = {64'h0000000000000000}; 226 localparam [63:0] MAINTENANCE168 = {64'h0000000000000000}; 227 localparam [63:0] MAINTENANCE169 = {64'h0000000000000000}; 228 localparam [63:0] MAINTENANCE170 = {64'h0000000000000000}; 229 localparam [63:0] MAINTENANCE171 = {64'h0000000000000000}; 230 localparam [63:0] MAINTENANCE172 = {64'h0000000000000000}; 231 localparam [63:0] MAINTENANCE173 = {64'h0000000000000000}; 232 localparam [63:0] MAINTENANCE174 = {64'h0000000000000000}; 233 localparam [63:0] MAINTENANCE175 = {64'h0000000000000000}; 234 localparam [63:0] MAINTENANCE176 = {64'h0000000000000000}; 235 localparam [63:0] MAINTENANCE177 = {64'h0000000000000000}; 236 localparam [63:0] MAINTENANCE178 = {64'h0000000000000000}; 237 localparam [63:0] MAINTENANCE179 = {64'h0000000000000000}; 238 localparam [63:0] MAINTENANCE180 = {64'h0000000000000000}; 239 localparam [63:0] MAINTENANCE181 = {64'h0000000000000000}; 240 localparam [63:0] MAINTENANCE182 = {64'h0000000000000000}; 241 localparam [63:0] MAINTENANCE183 = {64'h0000000000000000}; 242 localparam [63:0] MAINTENANCE184 = {64'h0000000000000000}; 243 localparam [63:0] MAINTENANCE185 = {64'h0000000000000000}; 244 localparam [63:0] MAINTENANCE186 = {64'h0000000000000000}; 245 localparam [63:0] MAINTENANCE187 = {64'h0000000000000000}; 246 localparam [63:0] MAINTENANCE188 = {64'h0000000000000000}; 247 localparam [63:0] MAINTENANCE189 = {64'h0000000000000000}; 248 localparam [63:0] MAINTENANCE190 = {64'h0000000000000000}; 249 localparam [63:0] MAINTENANCE191 = {64'h0000000000000000}; 250 localparam [63:0] MAINTENANCE192 = {64'h0000000000000000}; 251 localparam [63:0] MAINTENANCE193 = {64'h0000000000000000}; 252 localparam [63:0] MAINTENANCE194 = {64'h0000000000000000}; 253 localparam [63:0] MAINTENANCE195 = {64'h0000000000000000}; 254 localparam [63:0] MAINTENANCE196 = {64'h0000000000000000}; 255 localparam [63:0] MAINTENANCE197 = {64'h0000000000000000}; 256 localparam [63:0] MAINTENANCE198 = {64'h0000000000000000}; 257 localparam [63:0] MAINTENANCE199 = {64'h0000000000000000}; 258 localparam [63:0] MAINTENANCE200 = {64'h0000000000000000}; 259 localparam [63:0] MAINTENANCE201 = {64'h0000000000000000}; 260 localparam [63:0] MAINTENANCE202 = {64'h0000000000000000}; 261 localparam [63:0] MAINTENANCE203 = {64'h0000000000000000}; 262 localparam [63:0] MAINTENANCE204 = {64'h0000000000000000}; 263 localparam [63:0] MAINTENANCE205 = {64'h0000000000000000}; 264 localparam [63:0] MAINTENANCE206 = {64'h0000000000000000}; 265 localparam [63:0] MAINTENANCE207 = {64'h0000000000000000}; 266 localparam [63:0] MAINTENANCE208 = {64'h0000000000000000}; 267 localparam [63:0] MAINTENANCE209 = {64'h0000000000000000}; 268 localparam [63:0] MAINTENANCE210 = {64'h0000000000000000}; 269 localparam [63:0] MAINTENANCE211 = {64'h0000000000000000}; 270 localparam [63:0] MAINTENANCE212 = {64'h0000000000000000}; 271 localparam [63:0] MAINTENANCE213 = {64'h0000000000000000}; 272 localparam [63:0] MAINTENANCE214 = {64'h0000000000000000}; 273 localparam [63:0] MAINTENANCE215 = {64'h0000000000000000}; 274 localparam [63:0] MAINTENANCE216 = {64'h0000000000000000}; 275 localparam [63:0] MAINTENANCE217 = {64'h0000000000000000}; 276 localparam [63:0] MAINTENANCE218 = {64'h0000000000000000}; 277 localparam [63:0] MAINTENANCE219 = {64'h0000000000000000}; 278 localparam [63:0] MAINTENANCE220 = {64'h0000000000000000}; 279 localparam [63:0] MAINTENANCE221 = {64'h0000000000000000}; 280 localparam [63:0] MAINTENANCE222 = {64'h0000000000000000}; 281 localparam [63:0] MAINTENANCE223 = {64'h0000000000000000}; 282 localparam [63:0] MAINTENANCE224 = {64'h0000000000000000}; 283 localparam [63:0] MAINTENANCE225 = {64'h0000000000000000}; 284 localparam [63:0] MAINTENANCE226 = {64'h0000000000000000}; 285 localparam [63:0] MAINTENANCE227 = {64'h0000000000000000}; 286 localparam [63:0] MAINTENANCE228 = {64'h0000000000000000}; 287 localparam [63:0] MAINTENANCE229 = {64'h0000000000000000}; 288 localparam [63:0] MAINTENANCE230 = {64'h0000000000000000}; 289 localparam [63:0] MAINTENANCE231 = {64'h0000000000000000}; 290 localparam [63:0] MAINTENANCE232 = {64'h0000000000000000}; 291 localparam [63:0] MAINTENANCE233 = {64'h0000000000000000}; 292 localparam [63:0] MAINTENANCE234 = {64'h0000000000000000}; 293 localparam [63:0] MAINTENANCE235 = {64'h0000000000000000}; 294 localparam [63:0] MAINTENANCE236 = {64'h0000000000000000}; 295 localparam [63:0] MAINTENANCE237 = {64'h0000000000000000}; 296 localparam [63:0] MAINTENANCE238 = {64'h0000000000000000}; 297 localparam [63:0] MAINTENANCE239 = {64'h0000000000000000}; 298 localparam [63:0] MAINTENANCE240 = {64'h0000000000000000}; 299 localparam [63:0] MAINTENANCE241 = {64'h0000000000000000}; 300 localparam [63:0] MAINTENANCE242 = {64'h0000000000000000}; 301 localparam [63:0] MAINTENANCE243 = {64'h0000000000000000}; 302 localparam [63:0] MAINTENANCE244 = {64'h0000000000000000}; 303 localparam [63:0] MAINTENANCE245 = {64'h0000000000000000}; 304 localparam [63:0] MAINTENANCE246 = {64'h0000000000000000}; 305 localparam [63:0] MAINTENANCE247 = {64'h0000000000000000}; 306 localparam [63:0] MAINTENANCE248 = {64'h0000000000000000}; 307 localparam [63:0] MAINTENANCE249 = {64'h0000000000000000}; 308 localparam [63:0] MAINTENANCE250 = {64'h0000000000000000}; 309 localparam [63:0] MAINTENANCE251 = {64'h0000000000000000}; 310 localparam [63:0] MAINTENANCE252 = {64'h0000000000000000}; 311 localparam [63:0] MAINTENANCE253 = {64'h0000000000000000}; 312 localparam [63:0] MAINTENANCE254 = {64'h0000000000000000}; 313 localparam [63:0] MAINTENANCE255 = {64'h0000000000000000}; 314 localparam [63:0] MAINTENANCE256 = {64'h0000000000000000}; 315 localparam [63:0] MAINTENANCE257 = {64'h0000000000000000}; 316 localparam [63:0] MAINTENANCE258 = {64'h0000000000000000}; 317 localparam [63:0] MAINTENANCE259 = {64'h0000000000000000}; 318 localparam [63:0] MAINTENANCE260 = {64'h0000000000000000}; 319 localparam [63:0] MAINTENANCE261 = {64'h0000000000000000}; 320 localparam [63:0] MAINTENANCE262 = {64'h0000000000000000}; 321 localparam [63:0] MAINTENANCE263 = {64'h0000000000000000}; 322 localparam [63:0] MAINTENANCE264 = {64'h0000000000000000}; 323 localparam [63:0] MAINTENANCE265 = {64'h0000000000000000}; 324 localparam [63:0] MAINTENANCE266 = {64'h0000000000000000}; 325 localparam [63:0] MAINTENANCE267 = {64'h0000000000000000}; 326 localparam [63:0] MAINTENANCE268 = {64'h0000000000000000}; 327 localparam [63:0] MAINTENANCE269 = {64'h0000000000000000}; 328 localparam [63:0] MAINTENANCE270 = {64'h0000000000000000}; 329 localparam [63:0] MAINTENANCE271 = {64'h0000000000000000}; 330 localparam [63:0] MAINTENANCE272 = {64'h0000000000000000}; 331 localparam [63:0] MAINTENANCE273 = {64'h0000000000000000}; 332 localparam [63:0] MAINTENANCE274 = {64'h0000000000000000}; 333 localparam [63:0] MAINTENANCE275 = {64'h0000000000000000}; 334 localparam [63:0] MAINTENANCE276 = {64'h0000000000000000}; 335 localparam [63:0] MAINTENANCE277 = {64'h0000000000000000}; 336 localparam [63:0] MAINTENANCE278 = {64'h0000000000000000}; 337 localparam [63:0] MAINTENANCE279 = {64'h0000000000000000}; 338 localparam [63:0] MAINTENANCE280 = {64'h0000000000000000}; 339 localparam [63:0] MAINTENANCE281 = {64'h0000000000000000}; 340 localparam [63:0] MAINTENANCE282 = {64'h0000000000000000}; 341 localparam [63:0] MAINTENANCE283 = {64'h0000000000000000}; 342 localparam [63:0] MAINTENANCE284 = {64'h0000000000000000}; 343 localparam [63:0] MAINTENANCE285 = {64'h0000000000000000}; 344 localparam [63:0] MAINTENANCE286 = {64'h0000000000000000}; 345 localparam [63:0] MAINTENANCE287 = {64'h0000000000000000}; 346 localparam [63:0] MAINTENANCE288 = {64'h0000000000000000}; 347 localparam [63:0] MAINTENANCE289 = {64'h0000000000000000}; 348 localparam [63:0] MAINTENANCE290 = {64'h0000000000000000}; 349 localparam [63:0] MAINTENANCE291 = {64'h0000000000000000}; 350 localparam [63:0] MAINTENANCE292 = {64'h0000000000000000}; 351 localparam [63:0] MAINTENANCE293 = {64'h0000000000000000}; 352 localparam [63:0] MAINTENANCE294 = {64'h0000000000000000}; 353 localparam [63:0] MAINTENANCE295 = {64'h0000000000000000}; 354 localparam [63:0] MAINTENANCE296 = {64'h0000000000000000}; 355 localparam [63:0] MAINTENANCE297 = {64'h0000000000000000}; 356 localparam [63:0] MAINTENANCE298 = {64'h0000000000000000}; 357 localparam [63:0] MAINTENANCE299 = {64'h0000000000000000}; 358 localparam [63:0] MAINTENANCE300 = {64'h0000000000000000}; 359 localparam [63:0] MAINTENANCE301 = {64'h0000000000000000}; 360 localparam [63:0] MAINTENANCE302 = {64'h0000000000000000}; 361 localparam [63:0] MAINTENANCE303 = {64'h0000000000000000}; 362 localparam [63:0] MAINTENANCE304 = {64'h0000000000000000}; 363 localparam [63:0] MAINTENANCE305 = {64'h0000000000000000}; 364 localparam [63:0] MAINTENANCE306 = {64'h0000000000000000}; 365 localparam [63:0] MAINTENANCE307 = {64'h0000000000000000}; 366 localparam [63:0] MAINTENANCE308 = {64'h0000000000000000}; 367 localparam [63:0] MAINTENANCE309 = {64'h0000000000000000}; 368 localparam [63:0] MAINTENANCE310 = {64'h0000000000000000}; 369 localparam [63:0] MAINTENANCE311 = {64'h0000000000000000}; 370 localparam [63:0] MAINTENANCE312 = {64'h0000000000000000}; 371 localparam [63:0] MAINTENANCE313 = {64'h0000000000000000}; 372 localparam [63:0] MAINTENANCE314 = {64'h0000000000000000}; 373 localparam [63:0] MAINTENANCE315 = {64'h0000000000000000}; 374 localparam [63:0] MAINTENANCE316 = {64'h0000000000000000}; 375 localparam [63:0] MAINTENANCE317 = {64'h0000000000000000}; 376 localparam [63:0] MAINTENANCE318 = {64'h0000000000000000}; 377 localparam [63:0] MAINTENANCE319 = {64'h0000000000000000}; 378 localparam [63:0] MAINTENANCE320 = {64'h0000000000000000}; 379 localparam [63:0] MAINTENANCE321 = {64'h0000000000000000}; 380 localparam [63:0] MAINTENANCE322 = {64'h0000000000000000}; 381 localparam [63:0] MAINTENANCE323 = {64'h0000000000000000}; 382 localparam [63:0] MAINTENANCE324 = {64'h0000000000000000}; 383 localparam [63:0] MAINTENANCE325 = {64'h0000000000000000}; 384 localparam [63:0] MAINTENANCE326 = {64'h0000000000000000}; 385 localparam [63:0] MAINTENANCE327 = {64'h0000000000000000}; 386 localparam [63:0] MAINTENANCE328 = {64'h0000000000000000}; 387 localparam [63:0] MAINTENANCE329 = {64'h0000000000000000}; 388 localparam [63:0] MAINTENANCE330 = {64'h0000000000000000}; 389 localparam [63:0] MAINTENANCE331 = {64'h0000000000000000}; 390 localparam [63:0] MAINTENANCE332 = {64'h0000000000000000}; 391 localparam [63:0] MAINTENANCE333 = {64'h0000000000000000}; 392 localparam [63:0] MAINTENANCE334 = {64'h0000000000000000}; 393 localparam [63:0] MAINTENANCE335 = {64'h0000000000000000}; 394 localparam [63:0] MAINTENANCE336 = {64'h0000000000000000}; 395 localparam [63:0] MAINTENANCE337 = {64'h0000000000000000}; 396 localparam [63:0] MAINTENANCE338 = {64'h0000000000000000}; 397 localparam [63:0] MAINTENANCE339 = {64'h0000000000000000}; 398 localparam [63:0] MAINTENANCE340 = {64'h0000000000000000}; 399 localparam [63:0] MAINTENANCE341 = {64'h0000000000000000}; 400 localparam [63:0] MAINTENANCE342 = {64'h0000000000000000}; 401 localparam [63:0] MAINTENANCE343 = {64'h0000000000000000}; 402 localparam [63:0] MAINTENANCE344 = {64'h0000000000000000}; 403 localparam [63:0] MAINTENANCE345 = {64'h0000000000000000}; 404 localparam [63:0] MAINTENANCE346 = {64'h0000000000000000}; 405 localparam [63:0] MAINTENANCE347 = {64'h0000000000000000}; 406 localparam [63:0] MAINTENANCE348 = {64'h0000000000000000}; 407 localparam [63:0] MAINTENANCE349 = {64'h0000000000000000}; 408 localparam [63:0] MAINTENANCE350 = {64'h0000000000000000}; 409 localparam [63:0] MAINTENANCE351 = {64'h0000000000000000}; 410 localparam [63:0] MAINTENANCE352 = {64'h0000000000000000}; 411 localparam [63:0] MAINTENANCE353 = {64'h0000000000000000}; 412 localparam [63:0] MAINTENANCE354 = {64'h0000000000000000}; 413 localparam [63:0] MAINTENANCE355 = {64'h0000000000000000}; 414 localparam [63:0] MAINTENANCE356 = {64'h0000000000000000}; 415 localparam [63:0] MAINTENANCE357 = {64'h0000000000000000}; 416 localparam [63:0] MAINTENANCE358 = {64'h0000000000000000}; 417 localparam [63:0] MAINTENANCE359 = {64'h0000000000000000}; 418 localparam [63:0] MAINTENANCE360 = {64'h0000000000000000}; 419 localparam [63:0] MAINTENANCE361 = {64'h0000000000000000}; 420 localparam [63:0] MAINTENANCE362 = {64'h0000000000000000}; 421 localparam [63:0] MAINTENANCE363 = {64'h0000000000000000}; 422 localparam [63:0] MAINTENANCE364 = {64'h0000000000000000}; 423 localparam [63:0] MAINTENANCE365 = {64'h0000000000000000}; 424 localparam [63:0] MAINTENANCE366 = {64'h0000000000000000}; 425 localparam [63:0] MAINTENANCE367 = {64'h0000000000000000}; 426 localparam [63:0] MAINTENANCE368 = {64'h0000000000000000}; 427 localparam [63:0] MAINTENANCE369 = {64'h0000000000000000}; 428 localparam [63:0] MAINTENANCE370 = {64'h0000000000000000}; 429 localparam [63:0] MAINTENANCE371 = {64'h0000000000000000}; 430 localparam [63:0] MAINTENANCE372 = {64'h0000000000000000}; 431 localparam [63:0] MAINTENANCE373 = {64'h0000000000000000}; 432 localparam [63:0] MAINTENANCE374 = {64'h0000000000000000}; 433 localparam [63:0] MAINTENANCE375 = {64'h0000000000000000}; 434 localparam [63:0] MAINTENANCE376 = {64'h0000000000000000}; 435 localparam [63:0] MAINTENANCE377 = {64'h0000000000000000}; 436 localparam [63:0] MAINTENANCE378 = {64'h0000000000000000}; 437 localparam [63:0] MAINTENANCE379 = {64'h0000000000000000}; 438 localparam [63:0] MAINTENANCE380 = {64'h0000000000000000}; 439 localparam [63:0] MAINTENANCE381 = {64'h0000000000000000}; 440 localparam [63:0] MAINTENANCE382 = {64'h0000000000000000}; 441 localparam [63:0] MAINTENANCE383 = {64'h0000000000000000}; 442 localparam [63:0] MAINTENANCE384 = {64'h0000000000000000}; 443 localparam [63:0] MAINTENANCE385 = {64'h0000000000000000}; 444 localparam [63:0] MAINTENANCE386 = {64'h0000000000000000}; 445 localparam [63:0] MAINTENANCE387 = {64'h0000000000000000}; 446 localparam [63:0] MAINTENANCE388 = {64'h0000000000000000}; 447 localparam [63:0] MAINTENANCE389 = {64'h0000000000000000}; 448 localparam [63:0] MAINTENANCE390 = {64'h0000000000000000}; 449 localparam [63:0] MAINTENANCE391 = {64'h0000000000000000}; 450 localparam [63:0] MAINTENANCE392 = {64'h0000000000000000}; 451 localparam [63:0] MAINTENANCE393 = {64'h0000000000000000}; 452 localparam [63:0] MAINTENANCE394 = {64'h0000000000000000}; 453 localparam [63:0] MAINTENANCE395 = {64'h0000000000000000}; 454 localparam [63:0] MAINTENANCE396 = {64'h0000000000000000}; 455 localparam [63:0] MAINTENANCE397 = {64'h0000000000000000}; 456 localparam [63:0] MAINTENANCE398 = {64'h0000000000000000}; 457 localparam [63:0] MAINTENANCE399 = {64'h0000000000000000}; 458 localparam [63:0] MAINTENANCE400 = {64'h0000000000000000}; 459 localparam [63:0] MAINTENANCE401 = {64'h0000000000000000}; 460 localparam [63:0] MAINTENANCE402 = {64'h0000000000000000}; 461 localparam [63:0] MAINTENANCE403 = {64'h0000000000000000}; 462 localparam [63:0] MAINTENANCE404 = {64'h0000000000000000}; 463 localparam [63:0] MAINTENANCE405 = {64'h0000000000000000}; 464 localparam [63:0] MAINTENANCE406 = {64'h0000000000000000}; 465 localparam [63:0] MAINTENANCE407 = {64'h0000000000000000}; 466 localparam [63:0] MAINTENANCE408 = {64'h0000000000000000}; 467 localparam [63:0] MAINTENANCE409 = {64'h0000000000000000}; 468 localparam [63:0] MAINTENANCE410 = {64'h0000000000000000}; 469 localparam [63:0] MAINTENANCE411 = {64'h0000000000000000}; 470 localparam [63:0] MAINTENANCE412 = {64'h0000000000000000}; 471 localparam [63:0] MAINTENANCE413 = {64'h0000000000000000}; 472 localparam [63:0] MAINTENANCE414 = {64'h0000000000000000}; 473 localparam [63:0] MAINTENANCE415 = {64'h0000000000000000}; 474 localparam [63:0] MAINTENANCE416 = {64'h0000000000000000}; 475 localparam [63:0] MAINTENANCE417 = {64'h0000000000000000}; 476 localparam [63:0] MAINTENANCE418 = {64'h0000000000000000}; 477 localparam [63:0] MAINTENANCE419 = {64'h0000000000000000}; 478 localparam [63:0] MAINTENANCE420 = {64'h0000000000000000}; 479 localparam [63:0] MAINTENANCE421 = {64'h0000000000000000}; 480 localparam [63:0] MAINTENANCE422 = {64'h0000000000000000}; 481 localparam [63:0] MAINTENANCE423 = {64'h0000000000000000}; 482 localparam [63:0] MAINTENANCE424 = {64'h0000000000000000}; 483 localparam [63:0] MAINTENANCE425 = {64'h0000000000000000}; 484 localparam [63:0] MAINTENANCE426 = {64'h0000000000000000}; 485 localparam [63:0] MAINTENANCE427 = {64'h0000000000000000}; 486 localparam [63:0] MAINTENANCE428 = {64'h0000000000000000}; 487 localparam [63:0] MAINTENANCE429 = {64'h0000000000000000}; 488 localparam [63:0] MAINTENANCE430 = {64'h0000000000000000}; 489 localparam [63:0] MAINTENANCE431 = {64'h0000000000000000}; 490 localparam [63:0] MAINTENANCE432 = {64'h0000000000000000}; 491 localparam [63:0] MAINTENANCE433 = {64'h0000000000000000}; 492 localparam [63:0] MAINTENANCE434 = {64'h0000000000000000}; 493 localparam [63:0] MAINTENANCE435 = {64'h0000000000000000}; 494 localparam [63:0] MAINTENANCE436 = {64'h0000000000000000}; 495 localparam [63:0] MAINTENANCE437 = {64'h0000000000000000}; 496 localparam [63:0] MAINTENANCE438 = {64'h0000000000000000}; 497 localparam [63:0] MAINTENANCE439 = {64'h0000000000000000}; 498 localparam [63:0] MAINTENANCE440 = {64'h0000000000000000}; 499 localparam [63:0] MAINTENANCE441 = {64'h0000000000000000}; 500 localparam [63:0] MAINTENANCE442 = {64'h0000000000000000}; 501 localparam [63:0] MAINTENANCE443 = {64'h0000000000000000}; 502 localparam [63:0] MAINTENANCE444 = {64'h0000000000000000}; 503 localparam [63:0] MAINTENANCE445 = {64'h0000000000000000}; 504 localparam [63:0] MAINTENANCE446 = {64'h0000000000000000}; 505 localparam [63:0] MAINTENANCE447 = {64'h0000000000000000}; 506 localparam [63:0] MAINTENANCE448 = {64'h0000000000000000}; 507 localparam [63:0] MAINTENANCE449 = {64'h0000000000000000}; 508 localparam [63:0] MAINTENANCE450 = {64'h0000000000000000}; 509 localparam [63:0] MAINTENANCE451 = {64'h0000000000000000}; 510 localparam [63:0] MAINTENANCE452 = {64'h0000000000000000}; 511 localparam [63:0] MAINTENANCE453 = {64'h0000000000000000}; 512 localparam [63:0] MAINTENANCE454 = {64'h0000000000000000}; 513 localparam [63:0] MAINTENANCE455 = {64'h0000000000000000}; 514 localparam [63:0] MAINTENANCE456 = {64'h0000000000000000}; 515 localparam [63:0] MAINTENANCE457 = {64'h0000000000000000}; 516 localparam [63:0] MAINTENANCE458 = {64'h0000000000000000}; 517 localparam [63:0] MAINTENANCE459 = {64'h0000000000000000}; 518 localparam [63:0] MAINTENANCE460 = {64'h0000000000000000}; 519 localparam [63:0] MAINTENANCE461 = {64'h0000000000000000}; 520 localparam [63:0] MAINTENANCE462 = {64'h0000000000000000}; 521 localparam [63:0] MAINTENANCE463 = {64'h0000000000000000}; 522 localparam [63:0] MAINTENANCE464 = {64'h0000000000000000}; 523 localparam [63:0] MAINTENANCE465 = {64'h0000000000000000}; 524 localparam [63:0] MAINTENANCE466 = {64'h0000000000000000}; 525 localparam [63:0] MAINTENANCE467 = {64'h0000000000000000}; 526 localparam [63:0] MAINTENANCE468 = {64'h0000000000000000}; 527 localparam [63:0] MAINTENANCE469 = {64'h0000000000000000}; 528 localparam [63:0] MAINTENANCE470 = {64'h0000000000000000}; 529 localparam [63:0] MAINTENANCE471 = {64'h0000000000000000}; 530 localparam [63:0] MAINTENANCE472 = {64'h0000000000000000}; 531 localparam [63:0] MAINTENANCE473 = {64'h0000000000000000}; 532 localparam [63:0] MAINTENANCE474 = {64'h0000000000000000}; 533 localparam [63:0] MAINTENANCE475 = {64'h0000000000000000}; 534 localparam [63:0] MAINTENANCE476 = {64'h0000000000000000}; 535 localparam [63:0] MAINTENANCE477 = {64'h0000000000000000}; 536 localparam [63:0] MAINTENANCE478 = {64'h0000000000000000}; 537 localparam [63:0] MAINTENANCE479 = {64'h0000000000000000}; 538 localparam [63:0] MAINTENANCE480 = {64'h0000000000000000}; 539 localparam [63:0] MAINTENANCE481 = {64'h0000000000000000}; 540 localparam [63:0] MAINTENANCE482 = {64'h0000000000000000}; 541 localparam [63:0] MAINTENANCE483 = {64'h0000000000000000}; 542 localparam [63:0] MAINTENANCE484 = {64'h0000000000000000}; 543 localparam [63:0] MAINTENANCE485 = {64'h0000000000000000}; 544 localparam [63:0] MAINTENANCE486 = {64'h0000000000000000}; 545 localparam [63:0] MAINTENANCE487 = {64'h0000000000000000}; 546 localparam [63:0] MAINTENANCE488 = {64'h0000000000000000}; 547 localparam [63:0] MAINTENANCE489 = {64'h0000000000000000}; 548 localparam [63:0] MAINTENANCE490 = {64'h0000000000000000}; 549 localparam [63:0] MAINTENANCE491 = {64'h0000000000000000}; 550 localparam [63:0] MAINTENANCE492 = {64'h0000000000000000}; 551 localparam [63:0] MAINTENANCE493 = {64'h0000000000000000}; 552 localparam [63:0] MAINTENANCE494 = {64'h0000000000000000}; 553 localparam [63:0] MAINTENANCE495 = {64'h0000000000000000}; 554 localparam [63:0] MAINTENANCE496 = {64'h0000000000000000}; 555 localparam [63:0] MAINTENANCE497 = {64'h0000000000000000}; 556 localparam [63:0] MAINTENANCE498 = {64'h0000000000000000}; 557 localparam [63:0] MAINTENANCE499 = {64'h0000000000000000}; 558 localparam [63:0] MAINTENANCE500 = {64'h0000000000000000}; 559 localparam [63:0] MAINTENANCE501 = {64'h0000000000000000}; 560 localparam [63:0] MAINTENANCE502 = {64'h0000000000000000}; 561 localparam [63:0] MAINTENANCE503 = {64'h0000000000000000}; 562 localparam [63:0] MAINTENANCE504 = {64'h0000000000000000}; 563 localparam [63:0] MAINTENANCE505 = {64'h0000000000000000}; 564 localparam [63:0] MAINTENANCE506 = {64'h0000000000000000}; 565 localparam [63:0] MAINTENANCE507 = {64'h0000000000000000}; 566 localparam [63:0] MAINTENANCE508 = {64'h0000000000000000}; 567 localparam [63:0] MAINTENANCE509 = {64'h0000000000000000}; 568 localparam [63:0] MAINTENANCE510 = {64'h0000000000000000}; 569 localparam [63:0] MAINTENANCE511 = {64'h0000000000000000}; 570 571 572 // }}} End local parameters -------------
instruction_list.vh源码
1 localparam NUM_SWRITES = SEND_SWRITE ? 37 : 0; 2 localparam NUM_NWRITERS = SEND_NWRITER ? 19 : 0; 3 localparam NUM_NWRITES = SEND_NWRITE ? 19 : 0; 4 localparam NUM_NREADS = SEND_NREAD ? 26 : 0; 5 localparam NUM_DBS = SEND_DB ? 2 : 0; 6 localparam NUM_MSGS = SEND_MSG ? 17 : 0; 7 localparam NUM_FTYPE9 = SEND_FTYPE9 ? 1 : 0; 8 9 localparam NUMBER_OF_INSTRUCTIONS = NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS + NUM_DBS + NUM_MSGS + NUM_FTYPE9; 10 11 localparam [64*37-1:0] swrite_instruction = { 12 // RSVD, FTYPE, TTYPE, ADDRESS, SIZE 13 // SWRITEs 14 {12'h000, SWRITE, 4'h0, 36'h000000777, 8'd0}, 15 {12'h000, SWRITE, 4'h0, 36'h000008806, 8'd0}, 16 {12'h000, SWRITE, 4'h0, 36'h000000125, 8'd0}, 17 {12'h000, SWRITE, 4'h0, 36'h000000124, 8'd0}, 18 {12'h000, SWRITE, 4'h0, 36'h000000123, 8'd0}, 19 {12'h000, SWRITE, 4'h0, 36'h000000122, 8'd0}, 20 {12'h000, SWRITE, 4'h0, 36'h000000121, 8'd0}, 21 {12'h000, SWRITE, 4'h0, 36'h000000120, 8'd0}, 22 {12'h000, SWRITE, 4'h0, 36'h000000126, 8'd1}, 23 {12'h000, SWRITE, 4'h0, 36'h000000124, 8'd1}, 24 {12'h000, SWRITE, 4'h0, 36'h000000122, 8'd1}, 25 {12'h000, SWRITE, 4'h0, 36'h000004350, 8'd1}, 26 {12'h000, SWRITE, 4'h0, 36'h000004355, 8'd2}, 27 {12'h000, SWRITE, 4'h0, 36'h000012300, 8'd2}, 28 {12'h000, SWRITE, 4'h0, 36'h000012304, 8'd3}, 29 {12'h000, SWRITE, 4'h0, 36'h000345000, 8'd3}, 30 {12'h000, SWRITE, 4'h0, 36'h000345003, 8'd4}, 31 {12'h000, SWRITE, 4'h0, 36'h004550000, 8'd4}, 32 {12'h000, SWRITE, 4'h0, 36'h004550002, 8'd5}, 33 {12'h000, SWRITE, 4'h0, 36'h198877600, 8'd5}, 34 {12'h000, SWRITE, 4'h0, 36'h198877601, 8'd6}, 35 {12'h000, SWRITE, 4'h0, 36'h2ABBCCDD8, 8'd6}, 36 {12'h000, SWRITE, 4'h0, 36'h2ABBCCDD8, 8'd7}, 37 {12'h000, SWRITE, 4'h0, 36'h2ABBCCDD8, 8'd15}, 38 {12'h000, SWRITE, 4'h0, 36'h2ABBCCDD8, 8'd31}, 39 {12'h000, SWRITE, 4'h0, 36'h120000600, 8'd63}, 40 {12'h000, SWRITE, 4'h0, 36'h230000600, 8'd95}, 41 {12'h000, SWRITE, 4'h0, 36'h340000600, 8'd127}, 42 {12'h000, SWRITE, 4'h0, 36'h450000600, 8'd255}, 43 {12'h000, SWRITE, 4'h0, 36'h560000600, 8'd15}, 44 {12'h000, SWRITE, 4'h0, 36'h670000600, 8'd31}, 45 {12'h000, SWRITE, 4'h0, 36'h780000600, 8'd63}, 46 {12'h000, SWRITE, 4'h0, 36'h780000600, 8'd95}, 47 {12'h000, SWRITE, 4'h0, 36'h890000600, 8'd127}, 48 {12'h000, SWRITE, 4'h0, 36'h9A0000600, 8'd255}, 49 {12'h000, SWRITE, 4'h0, 36'hAB0000600, 8'd15}, 50 {12'h000, SWRITE, 4'h0, 36'hCD0000600, 8'd15}}; 51 52 localparam [64*19-1:0] nwriter_instruction = { 53 // NWRITERs 54 {12'h000, NWRITE, TNWR_R, 36'h000000777, 8'd0}, 55 {12'h000, NWRITE, TNWR_R, 36'h000008806, 8'd0}, 56 {12'h000, NWRITE, TNWR_R, 36'h000000125, 8'd0}, 57 {12'h000, NWRITE, TNWR_R, 36'h000000124, 8'd0}, 58 {12'h000, NWRITE, TNWR_R, 36'h000000123, 8'd0}, 59 {12'h000, NWRITE, TNWR_R, 36'h000000122, 8'd0}, 60 {12'h000, NWRITE, TNWR_R, 36'h000000121, 8'd0}, 61 {12'h000, NWRITE, TNWR_R, 36'h000000120, 8'd0}, 62 {12'h000, NWRITE, TNWR_R, 36'h000000126, 8'd1}, 63 {12'h000, NWRITE, TNWR_R, 36'h000000124, 8'd1}, 64 {12'h000, NWRITE, TNWR_R, 36'h000000122, 8'd1}, 65 {12'h000, NWRITE, TNWR_R, 36'h000004350, 8'd1}, 66 {12'h000, NWRITE, TNWR_R, 36'h000004355, 8'd2}, 67 {12'h000, NWRITE, TNWR_R, 36'h000012300, 8'd2}, 68 {12'h000, NWRITE, TNWR_R, 36'h000012304, 8'd3}, 69 {12'h000, NWRITE, TNWR_R, 36'h000345000, 8'd3}, 70 {12'h000, NWRITE, TNWR_R, 36'h000345003, 8'd4}, 71 {12'h000, NWRITE, TNWR_R, 36'h004550000, 8'd4}, 72 {12'h000, NWRITE, TNWR_R, 36'h004550002, 8'd5}}; 73 74 localparam [64*19-1:0] nwrite_instruction = { 75 // NWRITEs 76 {12'h000, NWRITE, TNWR, 36'h198877600, 8'd5}, 77 {12'h000, NWRITE, TNWR, 36'h198877601, 8'd6}, 78 {12'h000, NWRITE, TNWR, 36'h2ABBCCDD8, 8'd6}, 79 {12'h000, NWRITE, TNWR, 36'h2ABBCCDD8, 8'd7}, 80 {12'h000, NWRITE, TNWR, 36'h2ABBCCDD8, 8'd15}, 81 {12'h000, NWRITE, TNWR, 36'h2ABBCCDD8, 8'd31}, 82 {12'h000, NWRITE, TNWR, 36'h120000600, 8'd63}, 83 {12'h000, NWRITE, TNWR, 36'h230000600, 8'd95}, 84 {12'h000, NWRITE, TNWR, 36'h340000600, 8'd127}, 85 {12'h000, NWRITE, TNWR, 36'h450000600, 8'd255}, 86 {12'h000, NWRITE, TNWR, 36'h560000600, 8'd15}, 87 {12'h000, NWRITE, TNWR, 36'h670000600, 8'd31}, 88 {12'h000, NWRITE, TNWR, 36'h780000600, 8'd63}, 89 {12'h000, NWRITE, TNWR, 36'h890000600, 8'd95}, 90 {12'h000, NWRITE, TNWR, 36'h9A0000600, 8'd127}, 91 {12'h000, NWRITE, TNWR, 36'hAB0000600, 8'd255}, 92 {12'h000, NWRITE, TNWR, 36'hBC0000600, 8'd15}, 93 {12'h000, NWRITE, TNWR, 36'hCD0000600, 8'd15}, 94 {12'h000, NWRITE, TNWR, 36'hDE0000600, 8'd15}}; 95 96 localparam [64*26-1:0] nread_instruction = { 97 // NREADs 98 {12'h000, NREAD, TNRD, 36'h000002307, 8'd00}, 99 {12'h000, NREAD, TNRD, 36'h000002406, 8'd00}, 100 {12'h000, NREAD, TNRD, 36'h000002505, 8'd00}, 101 {12'h000, NREAD, TNRD, 36'h000002604, 8'd00}, 102 {12'h000, NREAD, TNRD, 36'h000002703, 8'd00}, 103 {12'h000, NREAD, TNRD, 36'h000002802, 8'd00}, 104 {12'h000, NREAD, TNRD, 36'h000002301, 8'd00}, 105 {12'h000, NREAD, TNRD, 36'h000002400, 8'd00}, 106 {12'h000, NREAD, TNRD, 36'h000002506, 8'd01}, 107 {12'h000, NREAD, TNRD, 36'h000002604, 8'd01}, 108 {12'h000, NREAD, TNRD, 36'h000002702, 8'd01}, 109 {12'h000, NREAD, TNRD, 36'h000002800, 8'd01}, 110 {12'h000, NREAD, TNRD, 36'h000002305, 8'd02}, 111 {12'h000, NREAD, TNRD, 36'h000002400, 8'd02}, 112 {12'h000, NREAD, TNRD, 36'h000002504, 8'd03}, 113 {12'h000, NREAD, TNRD, 36'h000002600, 8'd03}, 114 {12'h000, NREAD, TNRD, 36'h000002703, 8'd04}, 115 {12'h000, NREAD, TNRD, 36'h000002800, 8'd04}, 116 {12'h000, NREAD, TNRD, 36'h000002502, 8'd05}, 117 {12'h000, NREAD, TNRD, 36'h000002600, 8'd05}, 118 {12'h000, NREAD, TNRD, 36'h000002701, 8'd06}, 119 {12'h000, NREAD, TNRD, 36'h000002800, 8'd06}, 120 {12'h000, NREAD, TNRD, 36'h0000023F0, 8'd07}, 121 {12'h000, NREAD, TNRD, 36'h000002400, 8'd15}, 122 {12'h000, NREAD, TNRD, 36'h000002500, 8'd31}, 123 {12'h000, NREAD, TNRD, 36'h000002600, 8'd63}}; 124 125 localparam [64*2-1:0] db_instruction = { 126 // DOORBELLs 127 {12'h000, DOORB, 4'b0, 36'h0DBDB0000, 8'd01}, 128 {12'h000, DOORB, 4'b0, 36'h044440000, 8'd01}}; 129 130 localparam [64*17-1:0] msg_instruction = { 131 // MESSAGEs 132 {12'h000, MESSG, 4'b0, 36'h000000002, 8'd07}, 133 {12'h000, MESSG, 4'b0, 36'h000000012, 8'd07}, 134 {12'h000, MESSG, 4'b0, 36'h000000022, 8'd07}, 135 {12'h000, MESSG, 4'b0, 36'h000000002, 8'd07}, 136 {12'h000, MESSG, 4'b0, 36'h000000012, 8'd07}, 137 {12'h000, MESSG, 4'b0, 36'h000000022, 8'd07}, 138 {12'h000, MESSG, 4'b0, 36'h000000002, 8'd07}, 139 {12'h000, MESSG, 4'b0, 36'h000000012, 8'd07}, 140 {12'h000, MESSG, 4'b0, 36'h000000022, 8'd07}, 141 {12'h000, MESSG, 4'b0, 36'h000000002, 8'd07}, 142 {12'h000, MESSG, 4'b0, 36'h000000012, 8'd07}, 143 {12'h000, MESSG, 4'b0, 36'h000000022, 8'd07}, 144 {12'h000, MESSG, 4'b0, 36'h000000002, 8'd07}, 145 {12'h000, MESSG, 4'b0, 36'h000000012, 8'd07}, 146 {12'h000, MESSG, 4'b0, 36'h000000022, 8'd07}, 147 {12'h000, MESSG, 4'b0, 36'h000000002, 8'd07}, 148 {12'h000, MESSG, 4'b0, 36'h000000012, 8'd07}}; 149 150 localparam [64*1-1:0] ftype9_instruction = { 151 // FTYPE9 152 {12'h000, FTYPE9, 4'b0, 36'h0DBDB1000, 8'd7}}; 153 // {{{ DISCLAIMER OF LIABILITY 154 // ----------------------------------------------------------------- 155 // (c) Copyright 2012 Xilinx, Inc. All rights reserved. 156 // 157 // This file contains confidential and proprietary information 158 // of Xilinx, Inc. and is protected under U.S. and 159 // international copyright and other intellectual property 160 // laws. 161 // 162 // DISCLAIMER 163 // This disclaimer is not a license and does not grant any 164 // rights to the materials distributed herewith. Except as 165 // otherwise provided in a valid license issued to you by 166 // Xilinx, and to the maximum extent permitted by applicable 167 // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 168 // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 169 // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 170 // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 171 // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 172 // (2) Xilinx shall not be liable (whether in contract or tort, 173 // including negligence, or under any other theory of 174 // liability) for any loss or damage of any kind or nature 175 // related to, arising under or in connection with these 176 // materials, including for any direct, or any indirect, 177 // special, incidental, or consequential loss or damage 178 // (including loss of data, profits, goodwill, or any type of 179 // loss or damage suffered as a result of any action brought 180 // by a third party) even if such damage or loss was 181 // reasonably foreseeable or Xilinx had been advised of the 182 // possibility of the same. 183 // 184 // CRITICAL APPLICATIONS 185 // Xilinx products are not designed or intended to be fail- 186 // safe, or for use in any application requiring fail-safe 187 // performance, such as life-support or safety devices or 188 // systems, Class III medical devices, nuclear facilities, 189 // applications related to the deployment of airbags, or any 190 // other applications that could lead to death, personal 191 // injury, or severe property or environmental damage 192 // (individually and collectively, "Critical 193 // Applications"). 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八、参考资料
1、pg007_srio_gen2，下载地址： https://china.xilinx.com/support/documentation/ip_documentation/srio_gen2/v4_0/pg007_srio_gen2.pdf
2、ug190 ，下载地址：https://www.xilinx.com/support/documentation/user_guides/ug190.pdf
3、pg058-blk-mem-gen ， 下载地址：https://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_3/pg058-blk-mem-gen.pdf
4、Vivado2015.4.2 SRIO例子工程源码
