testbench基础

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module tb_s2p();
  reg clk;
  reg rstn;
  reg en;
  reg din;
  wire [7:0] dout;

  parameter CLK_PERIOD = 20;

  initial begin
    clk <= 1'b0;
    forever #(CLK_PERIOD / 2) clk <= ~clk;
  end
  
  initial begin
    $display("---------------------------");
    $display("[%0t] TB_INFO: Simulation Started.", $time);
    $display("---------------------------");

    initialize_signals();
    apply_reset();
    apply_en();
    send_data(8'hff);
    #40
    send_data(8'h0b);

    $diaplay("---------------------------");
    $display("[%0t] TB_INFO: Test finish! Simulation Stopped.", $time);
    $diaplay("---------------------------");  

    #40
    $finish;  
  end

  task initialize_signals;
    begin
      din <= 1'b0;
    end
  endtask

  task apply_reset;
    begin
      $display("[%0t] TB_INFO: Apllying hardware reset...", $time);
      rstn <= 1'b0;
      #(CLK_PERIOD * 5);
      rstn <= 1'b1;
      #(CLK_PERIOD);
      $display("[%0t] TB_INFO: Hardware reset released.", $time);
    end
  endtask

  task apply_en;
    begin
      en <= 1'b0;
      #(CLK_PERIOD * 2);
      en <= 1'b1;
    end
  endtask

  task send_data;
    input [7:0] data_to_send;
    integer  i;
    begin
      $display("[%0t] TB_INFO: Send data...0x%h", $time, data_to_send);
      @(posedge clk);
      din <= 1'b0;
      @(posedge clk);
      
      for(i=0; i<8;i++)begin
        din <= data_to_send[i];
        @(posedge clk);
      end
      din <= 1'b0;
      #CLK_PERIOD;
   end
  endtask

  `ifdef FSDB
    initial begin
      $fsdbDumpfile("waveform.fsdb");
      $fsdbDumpvars;
    end
  `elsif VCDPLUS
    initial begin
      $vcdplusfile("waveform.vpd");
      $vcdpluson;
    end
  `endif

  s2p u_s2p
  (
    .clk    (clk ),
    .rstn   (rstn),
    .en     (en  ),
    .din    (din ),
    .dout   (dout) 
  );

endmodule

主要是使用task函数send_data,发送一串数据