FPGA中顶层模块与各子模块之间的连接线类型

顶层模块：mix_module

module mix_module
(
CLK, RSTn, Flash_LED, Run_LED
);

input CLK;
input RSTn;
output Flash_LED;
output [2:0]Run_LED;

/**********************************/

//wire Flash_LED;
//reg Flash_LED;

flash_module U1
(
.CLK( CLK ),
.RSTn( RSTn ),
.LED_Out( Flash_LED )
);

/**********************************/

//wire [2:0]Run_LED;
//reg [2:0]Run_LED;

run_module U2
(
.CLK( CLK ),
.RSTn( RSTn ),
.LED_Out( Run_LED )
);

/***********************************/

//assign Flash_LED = Flash_LED;
// assign Run_LED = Run_LED;

/**********************************/

endmodule

 

子模块1：flash_module

module flash_module
(
CLK, RSTn, LED_Out
);

input CLK;
input RSTn;
output reg LED_Out;

/*********************************/

parameter T50MS = 22'd2_499_999;//DB4CE15使用的晶振为50MHz，50M*0.05-1=2_499_999

/********************************/

reg [21:0]Count1;

always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 22'd0;
else if( Count1 == T50MS )
Count1 <= 22'd0;
else
Count1 <= Count1 + 1'b1;

/*********************************/

//reg rLED_Out;

always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
LED_Out <= 1'b0;
else if( Count1 == T50MS )
LED_Out <= ~LED_Out;

/*********************************/

//assign LED_Out = rLED_Out;

endmodule

 

子模块2：run_module

module run_module
(
CLK, RSTn, LED_Out
);

input CLK;
input RSTn;
output [2:0]LED_Out;

/**************************/

parameter T1MS = 16'd49_999;//DB4CE15使用的晶振为50MHz，50M*0.001-1=49_999

/**************************/

reg [15:0]Count1;

always @ ( posedge CLK or negedge RSTn )//1ms计数器
if( !RSTn )
Count1 <= 16'd0;
else if( Count1 == T1MS )
Count1 <= 16'd0;
else
Count1 <= Count1 + 1'b1;

/*****************************************/

reg [9:0]Count_MS;

always @ ( posedge CLK or negedge RSTn )//100ms计数器
if( !RSTn )
Count_MS <= 10'd0;
else if( Count_MS == 10'd100 )
Count_MS <= 10'd0;
else if( Count1 == T1MS )
Count_MS <= Count_MS + 1'b1;

/*********************************/

reg [2:0]rLED_Out;

always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rLED_Out <= 3'b001;
else if( Count_MS == 10'd100 )
begin

if( rLED_Out == 3'b000 )
rLED_Out <= 3'b001;
else
rLED_Out <= { rLED_Out[1:0], 1'b0 };//向左移位1bit操作
end

/*****************************/

assign LED_Out = rLED_Out;

/*****************************/

endmodule