net10 模块top-down设计

底层模块　　例化到　　顶层模块　　

我们不希望用我们用户自定义的时钟做寄存器的触发，时序会变差。所以调用时钟模块　　　　尽量产生标志 而不是占空比为50%的方波

 

如果模块内部接口是输入 例化时连接可以是　　wire　　也可以是　　reg

如果模块内部接口是输出　　例化时必须连接　　wire

 

 

 

 

module    div(
    input    wire    clk,
    input    wire    rst,
    output    reg    po_flag);

reg    [1:0]    cnt;

always@(posedge    clk)
begin
    if(rst)
        cnt<=0;
        else if(cnt=='d3)
        cnt<=1'b0;
        else 
        cnt<=cnt+1'b1;
end

always@(posedge clk)
begin
    if(rst)
        po_flag<=0;
        else if(cnt==3)
        po_flag<=1;
        else begin
            po_flag<=0;
        end
end

endmodule

module    a_b(
    input    wire    clk,
    input    wire    rst,
    input    wire    po_a,
    input    wire    po_b,
    input    wire    pi_flag,
    output    reg        po_c);

always@(posedge    clk)
begin
    if(rst)
        po_c=0;
        else if(pi_flag) begin
            po_c<=po_a    & po_b;
        end
end

endmodule

module    top_down(
    input    wire    clk,
    input    wire    rst,
    input    wire    pi_a,
    input    wire    pi_b,
    output    wire    po_c    );

wire    flag;

div top_down_inst(
    .clk(clk),
    .rst(rst),
    .po_flag(flag));

a_b    top_down_inst2(
    .clk(clk),
    .rst(rst),
    .po_a(pi_a),
    .po_b(pi_b),
    .pi_flag(flag),
    .po_c(po_c));

endmodule

`timescale    1ns/1ns
module    tb_top();
reg    clk,rst;
reg    pi_a,pi_b;
wire    po_c;

initial
begin
    clk=0;
    rst=1;
    pi_a=0;
    pi_b=0;
    #100
    rst=0;
end

always #5    pi_a={$random}%2;
always #5    pi_b={$random}%2;
always #10    clk=~clk;

top_down    tb_top_inst(
    .clk(clk),
    .rst(rst),
    .pi_a(pi_a),
    .pi_b(pi_b),
    .po_c(po_c));

endmodule