net9 呼吸灯

module    pw_led(
    input    wire    clk,
    input    wire    rst,
    output    reg        led);

parameter sec2=2*5000;//0000;
parameter    oneport=sec2/1000;
reg[31:0]    clk_cnt;
reg[31:0]    pwl_cnt;
reg[31:0]    port;

always@(posedge clk)
begin
    if(rst)
    clk_cnt<=0;
    else if(clk_cnt==oneport) begin
        clk_cnt<=0;
    end
    else begin
        clk_cnt<=clk_cnt+1'b1;
    end
end

always @(posedge clk)
begin
    if(rst)
    port<=0;
    else 
        begin 
              if(port==10)
                  port<=0;

              else     if(clk_cnt==oneport)
            port<=port+1'b1;
            else 
            port<=port;
        end
end

always@(posedge clk)
begin
    if(rst)
    led<=0;
    else if(clk_cnt<port)
        led<=0;
        else begin
            led<=1;
        end
end

endmodule

自己写了一个  仿真结果问题挺多，，害

 

 

 

 

 老师的代码一　　只实现从亮到灭　　会有闪烁的一下 不平滑 只有一半

module    new_led(
    input    wire    clk,
    input    wire    rst_n,
    output    reg        led);

wire    rst;

reg    [31:0]    clk50mcnt;
reg    [31:0]    clk50mcnt_1000;
reg    [31:0]    pwm_cyc_cnt;


assign rst =~rst_n ;

always@(posedge    clk)
begin
    if(rst)
    clk50mcnt<=0;
    else if(clk50mcnt=='d99) begin
             clk50mcnt<=0;
    end
        else begin
            clk50mcnt<=clk50mcnt+1'b1;
        end
end

always@(posedge    clk)
begin
        if(rst)
        clk50mcnt_1000<=0;
        else if(clk50mcnt==99    &&    clk50mcnt_1000==999) begin
                clk50mcnt_1000<=0;
        end
        else if(clk50mcnt=='d99) begin
            clk50mcnt_1000<=clk50mcnt_1000+1'b1;
        end
end

always@(posedge clk)
begin
    if(rst)
    pwm_cyc_cnt<=0;
    else if(clk50mcnt=='d99    &&    clk50mcnt_1000=='d999    && pwm_cyc_cnt=='d999) begin
        pwm_cyc_cnt<=0;
    end
    else  if(clk50mcnt=='d99     &&    clk50mcnt_1000=='d999)begin
         pwm_cyc_cnt<=pwm_cyc_cnt+1'b1;
    end
end

assign led =    (clk50mcnt_1000<pwm_cyc_cnt)    ?    1:0 ;

endmodule

加一个pwm_flag

assign led = (pwm_flag==1'b0)?((clk50mcnt_1000<pwm_cyc_cnt) ? 1:0 ): ((clk50mcnt_1000<pwm_cyc_cnt) ? 1:0);

module    new_led(
    input    wire    clk,
    input    wire    rst_n,
    output    reg        led);

wire    rst;

reg    [31:0]    clk50mcnt;
reg    [31:0]    clk50mcnt_1000;
reg    [31:0]    pwm_cyc_cnt;
reg            pwm_flag;

assign rst =~rst_n ;

always@(posedge    clk)
begin
    if(rst)
    clk50mcnt<=0;
    else if(clk50mcnt=='d99) begin
             clk50mcnt<=0;
    end
        else begin
            clk50mcnt<=clk50mcnt+1'b1;
        end
end

always@(posedge    clk)
begin
        if(rst)
        clk50mcnt_1000<=0;
        else if(clk50mcnt==99    &&    clk50mcnt_1000==999) begin
                clk50mcnt_1000<=0;
        end
        else if(clk50mcnt=='d99) begin
            clk50mcnt_1000<=clk50mcnt_1000+1'b1;
        end
end

always@(posedge clk)
begin
    if(rst)
    pwm_cyc_cnt<=0;
    else if(clk50mcnt=='d99    &&    clk50mcnt_1000=='d999    && pwm_cyc_cnt=='d999) begin
        pwm_cyc_cnt<=0;
    end
    else  if(clk50mcnt=='d99     &&    clk50mcnt_1000=='d999)begin
         pwm_cyc_cnt<=pwm_cyc_cnt+1'b1;
    end
end

always@(posedge clk)
begin
    if(rst)
    pwm_flag<=0;
    else begin
        if(clk50mcnt=='d99    &&    clk50mcnt_1000=='d999    && pwm_cyc_cnt=='d999)
        pwm_flag<=~pwm_flag;
    end
end


assign led =    (pwm_flag==1'b0)?((clk50mcnt_1000<pwm_cyc_cnt)    ?    1:0 ):    ((clk50mcnt_1000<pwm_cyc_cnt)    ?    1:0);

endmodule