design seq1_b3 sta_label 0.0-1.0 0.0-1.0 1e-9

# clocks
# clockID clock_name period rise_edge fall_edge source
clockID CLK 1.0 0.0 0.5 CLK

# Instance pin data

# instance_pin rise_slew fall_slew min_rise_arrival max_rise_arrival min_fall_arrival max_fall_arrival clock_name is_clock
U05/U5/U3/U1/Z 0.01 0.01 0.3 0.7 0.3 0.7 CLK 0
U05/U5/U2/Z 0.01 0.01 0.9 1.1 0.9 1.1 CLK 0
U05/U4/U2/Z 0.01 0.01 2.5 2.7 2.5 2.7 CLK 0

posted on 2019-10-22 14:33  春风一郎  阅读(753)  评论(0)    收藏  举报