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ifndef RAS_REG_H

define RAS_REG_H

include <fwk_macros.h>

include <stdint.h>

/ggg =================================================================
ggg 1. Standard Arm RAS Register Definitions
ggg ================================================================= ggg/
struct ras_reg_std {
/ggg 0x00 - 0x0F: Hidden (Feature, Control) ggg/
uint32_t _reserved0[4];

/ggg 0x10 Status Register (KEEP) ggg/
FWK_RW uint32_t ERR_STATUS_L;
FWK_RW uint32_t ERR_STATUS_H;

/ggg 0x18 - 0x2F: Hidden (Addr, Misc0, Misc1) ggg/
uint32_t _reserved1[6];

};

/ggg --- ERR_STATUS Bit Definitions (Common) --- ggg/

define RAS_ERR_STATUS_AV_MASK (1ULL << 31)

define RAS_ERR_STATUS_V_MASK (1ULL << 30)

define RAS_ERR_STATUS_UE_MASK (1ULL << 29)

define RAS_ERR_STATUS_CE_MASK (0x3ULL << 24)

/ggg =================================================================
ggg 2. DCN (Data Center Network) Definitions
ggg ================================================================= ggg/
struct ras_reg_dcn {
struct ras_reg_std ras;
};

/ggg =================================================================
ggg 3. GIC-700 RAS Registers
ggg ================================================================= ggg/
struct ras_reg_gic_record {
/ggg 0x00 - 0x0F: Hidden (FR, CTLR) ggg/
uint32_t _reserved0[4];

/ggg 0x10 Status Register (KEEP) ggg/
FWK_RW uint32_t STATUS_L;
FWK_RW uint32_t STATUS_H;

/ggg 0x18 - 0x2F: Hidden (Addr, Misc0, Misc1) ggg/
uint32_t _reserved1[6];

/ggg Padding 0x30-0x3F ggg/
uint32_t _reserved2[4];       

};

define GIC_RAS_ERRGSR_OFFSET 0xE000

/ggg GICT_ERR Bit Definitions ggg/

define GICT_ERR_STATUS_V (1ULL << 30)

/ggg =================================================================
ggg 4. CMN S3 Node Structure
ggg ================================================================= ggg/
struct ras_reg_cmn {
/ggg 0x0000: Hidden (Node Info) - Discovery uses raw pointer ggg/
uint32_t _reserved0[2];

uint8_t  _padding[0xE000 - 8];             

/ggg 0xE000: Standard RAS (Only Status visible) ggg/
struct ras_reg_std ras;                    

};

/ggg =================================================================
ggg 5. Synopsys DDR5 (Enhanced ECC)
ggg ================================================================= ggg/
struct ras_reg_ddr {
/ggg 0x00: Hidden (ECC_CFG) ggg/
uint32_t _reserved0;

/ggg 0x04: Status (KEEP) ggg/
FWK_RW uint32_t ECC_STAT;          

/ggg 0x08 - 0x13: Hidden (Addr, Syndrome) ggg/
uint32_t _reserved1[3];

/ggg 0x14: Interrupt Status (KEEP - needed for check) ggg/
FWK_RW uint32_t RAS_INT_STAT;      

/ggg 0x18: Interrupt Clear (KEEP - needed for W1C) ggg/
FWK_RW uint32_t RAS_INT_CLR;       

/ggg Hidden Control ggg/
uint32_t _reserved2;      

/ggg Status (KEEP) ggg/
FWK_R  uint32_t ECCERRCNTSTAT;     

};

define DDR_ECC_STAT_PER_RANK_INTR_MASK 0x0000000F

define DDR_ECC_CTL_CLR_RANK_0 (1U << 16)

define DDR_ECC_CTL_CLR_RANK_1 (1U << 17)

define DDR_ECC_CTL_CLR_RANK_2 (1U << 18)

define DDR_ECC_CTL_CLR_RANK_3 (1U << 19)

/ggg =================================================================
ggg 6. Other IP Registers (MCP, PCIe)
ggg ================================================================= ggg/
struct ras_reg_parity {
FWK_RW uint32_t MEM_ERR_STATUS; /ggg KEEP ggg/
uint32_t _reserved0; /ggg Hidden Addr ggg/
FWK_RW uint32_t MEM_ERR_CLEAR; /ggg KEEP ggg/
};

struct ras_reg_pcie_aer {
uint32_t _reserved0; /ggg Hidden Cap Hdr ggg/
FWK_RW uint32_t UNCORR_ERR_STATUS; /ggg KEEP ggg/
uint32_t _reserved1[2]; /ggg Hidden Mask, Sev ggg/
FWK_RW uint32_t CORR_ERR_STATUS; /ggg KEEP ggg/
uint32_t _reserved2[9]; /ggg Hidden Mask, Adv, Log, Root... ggg/
};

struct ras_reg_pcie_vsec_rasdp {
uint32_t _reserved0[9]; /ggg Hidden Headers, Ctrl, Counts ggg/

/ggg KEEP: Needed for fatal check, effectively a status ggg/
FWK_R  uint32_t RASDP_UNCORR_ERROR_LOCATION; 

uint32_t _reserved1;

/ggg KEEP: Needed to clear error ggg/
FWK_RW uint32_t RASDP_ERROR_MODE_CLEAR;

uint32_t _reserved2[2];

};

endif /ggg RAS_REG_H ggg/